JPS62166643U - - Google Patents

Info

Publication number
JPS62166643U
JPS62166643U JP5355286U JP5355286U JPS62166643U JP S62166643 U JPS62166643 U JP S62166643U JP 5355286 U JP5355286 U JP 5355286U JP 5355286 U JP5355286 U JP 5355286U JP S62166643 U JPS62166643 U JP S62166643U
Authority
JP
Japan
Prior art keywords
leads
wiring board
printed wiring
lands
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5355286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5355286U priority Critical patent/JPS62166643U/ja
Publication of JPS62166643U publication Critical patent/JPS62166643U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本考案の実施例を説明する
図であり、第1図はFP形ICの第1の実施例を
示す部分斜視図、第2図は第1図に示すFP形I
Cが実装される印刷配線板の部分平面図、第3図
はFP形ICの第2の実施例を示す部分平面図、
第4図はFP形ICの第3の実施例を示す部分平
面図。第5図は従来のFP形ICを示す平面図で
あり、第6図は第5図に示すFP形ICが実装さ
れる印刷配線板の部分平面図。 10,10a,10b……フラツトパツケージ
IC、12,18,20……リード、13……印
刷配線板、14……ランド、15,19,21…
…先端部分。
1 to 4 are diagrams explaining embodiments of the present invention, in which FIG. 1 is a partial perspective view showing a first embodiment of an FP type IC, and FIG. 2 is a partial perspective view of the FP type IC shown in FIG. 1. I
FIG. 3 is a partial plan view showing a second embodiment of the FP type IC;
FIG. 4 is a partial plan view showing a third embodiment of the FP type IC. FIG. 5 is a plan view showing a conventional FP type IC, and FIG. 6 is a partial plan view of a printed wiring board on which the FP type IC shown in FIG. 5 is mounted. 10, 10a, 10b... Flat package IC, 12, 18, 20... Lead, 13... Printed wiring board, 14... Land, 15, 19, 21...
...Tip part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードの先端部分を印刷配線板のランドに当接
させて半田付けするフラツトパツケージICにお
いて、前記リードの夫々は、隣接するリードと異
なる長さで形成されていることを特徴とするフラ
ツトパツケージIC。
A flat package IC in which the tips of the leads are soldered by contacting the lands of a printed wiring board, wherein each of the leads is formed to have a length different from that of an adjacent lead. I.C.
JP5355286U 1986-04-11 1986-04-11 Pending JPS62166643U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5355286U JPS62166643U (en) 1986-04-11 1986-04-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5355286U JPS62166643U (en) 1986-04-11 1986-04-11

Publications (1)

Publication Number Publication Date
JPS62166643U true JPS62166643U (en) 1987-10-22

Family

ID=30879723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5355286U Pending JPS62166643U (en) 1986-04-11 1986-04-11

Country Status (1)

Country Link
JP (1) JPS62166643U (en)

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