JPS6287483U - - Google Patents

Info

Publication number
JPS6287483U
JPS6287483U JP17737785U JP17737785U JPS6287483U JP S6287483 U JPS6287483 U JP S6287483U JP 17737785 U JP17737785 U JP 17737785U JP 17737785 U JP17737785 U JP 17737785U JP S6287483 U JPS6287483 U JP S6287483U
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
package
flat package
flat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17737785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17737785U priority Critical patent/JPS6287483U/ja
Publication of JPS6287483U publication Critical patent/JPS6287483U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る印刷配線板の一実施例を
示す断面図、第2図は第1図の平面図、第3図は
本実施例による印刷配線板にフラツトパツケージ
ICを実装した状態を示す要部断面図、第4図は
本考案の他の実施例を示す要部断面図、第5図は
フラツトパツケージICを搭載する従来の印刷配
線板を示す要部斜視図、第6図はフラツトパツケ
ージICを従来の印刷配線板に実装した状態を示
す要部断面図、第7図は第6図の平面図である。 1……フラツトパツケージIC、1a……リー
ド電極、1b……フラツト部、2……印刷配線板
、3a……ランド。
Fig. 1 is a sectional view showing an embodiment of the printed wiring board according to the present invention, Fig. 2 is a plan view of Fig. 1, and Fig. 3 is a flat package IC mounted on the printed wiring board according to the present invention. FIG. 4 is a cross-sectional view of main parts showing another embodiment of the present invention; FIG. 5 is a perspective view of main parts showing a conventional printed wiring board on which a flat package IC is mounted; FIG. FIG. 6 is a sectional view of a main part showing a state in which a flat package IC is mounted on a conventional printed wiring board, and FIG. 7 is a plan view of FIG. 6. 1... Flat package IC, 1a... Lead electrode, 1b... Flat part, 2... Printed wiring board, 3a... Land.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フラツトパツケージICを搭載する印刷配線板
において、この印刷配線板に形成された前記フラ
ツトパツケージICのリード電極を接続するため
のランドを、このフラツトパツケージICのリー
ド電極のフラツト部よりフラツトパツケージIC
の本体側に伸して形成したことを特徴とする印刷
配線板。
In a printed wiring board on which a flat package IC is mounted, a land formed on the printed wiring board for connecting the lead electrode of the flat package IC is connected to a flat part of the lead electrode of the flat package IC. Package IC
A printed wiring board characterized in that it is formed by extending toward the main body side.
JP17737785U 1985-11-20 1985-11-20 Pending JPS6287483U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17737785U JPS6287483U (en) 1985-11-20 1985-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17737785U JPS6287483U (en) 1985-11-20 1985-11-20

Publications (1)

Publication Number Publication Date
JPS6287483U true JPS6287483U (en) 1987-06-04

Family

ID=31118523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17737785U Pending JPS6287483U (en) 1985-11-20 1985-11-20

Country Status (1)

Country Link
JP (1) JPS6287483U (en)

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