JPS61157369U - - Google Patents
Info
- Publication number
- JPS61157369U JPS61157369U JP4112485U JP4112485U JPS61157369U JP S61157369 U JPS61157369 U JP S61157369U JP 4112485 U JP4112485 U JP 4112485U JP 4112485 U JP4112485 U JP 4112485U JP S61157369 U JPS61157369 U JP S61157369U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- soldering
- leads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims description 5
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図はこの考案のプリント基板の実施例を示
す平面図、第２図は第１図のプリント基板にＩＣ
を取付けた平面図、第３図は第２図の側面図、第
４図は従来のプリント基板の平面図、第５図はフ
ラツトパツクＩＣの平面図、第６図は第５図の側
面図である。
１……プリント基板、２……半田付けパターン
、２ａ……両端の半田付けパターン、３……フラ
ツトパツクＩＣ、４……リード、４ａ……両端部
のリード。
Fig. 1 is a plan view showing an embodiment of the printed circuit board of this invention, and Fig. 2 is a plan view showing an embodiment of the printed circuit board of this invention.
Fig. 3 is a side view of Fig. 2, Fig. 4 is a plan view of a conventional printed circuit board, Fig. 5 is a plan view of a flat pack IC, and Fig. 6 is a side view of Fig. 5. be. 1... Printed circuit board, 2... Soldering pattern, 2a... Soldering pattern at both ends, 3... Flat pack IC, 4... Lead, 4a... Lead at both ends.
Claims (1)
と半田付けするための、これら各リードと対応す
る複数個の半田付けパターンを備えたプリント基
板において、前記複数個のリードのうちの両端部
の各リードに対応する半田付けパターンの大きさ
を、他の半田付けパターンよりも大きく形成した
ことを特徴とするプリント基板。 In a printed circuit board equipped with a plurality of soldering patterns corresponding to the plurality of leads arranged in parallel on a flat pack IC, each lead at both ends of the plurality of leads is soldered. A printed circuit board characterized in that a corresponding soldering pattern is formed larger in size than other soldering patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4112485U JPS61157369U (en) | 1985-03-22 | 1985-03-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4112485U JPS61157369U (en) | 1985-03-22 | 1985-03-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61157369U true JPS61157369U (en) | 1986-09-30 |
Family
ID=30550654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4112485U Pending JPS61157369U (en) | 1985-03-22 | 1985-03-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61157369U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015159253A (en) * | 2014-02-25 | 2015-09-03 | ファナック株式会社 | printed circuit board |
-
1985
- 1985-03-22 JP JP4112485U patent/JPS61157369U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015159253A (en) * | 2014-02-25 | 2015-09-03 | ファナック株式会社 | printed circuit board |
| US9872388B2 (en) | 2014-02-25 | 2018-01-16 | Fanuc Corporation | Printed wiring board |
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