JPS6265876U - - Google Patents

Info

Publication number
JPS6265876U
JPS6265876U JP15837285U JP15837285U JPS6265876U JP S6265876 U JPS6265876 U JP S6265876U JP 15837285 U JP15837285 U JP 15837285U JP 15837285 U JP15837285 U JP 15837285U JP S6265876 U JPS6265876 U JP S6265876U
Authority
JP
Japan
Prior art keywords
land
terminal
circuit board
printed circuit
flat package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15837285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15837285U priority Critical patent/JPS6265876U/ja
Publication of JPS6265876U publication Critical patent/JPS6265876U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例のプリント基板の
平面図、第2図は同実施例のプリント基板にフラ
ツトパツケージICを仮止めした状態を示す平面
図、第3図は従来例のプリント基板の平面図、第
4図は従来例のプリント基板にフラツトパツケー
ジICを仮止めした状態を示す平面図である。 1:半田溜用ランド、3:IC端子用ランド群
、3a:IC端子用ランド、4:フラツトパツケ
ージIC、5:IC端子群、5a:IC端子。
Fig. 1 is a plan view of a printed circuit board according to an embodiment of this invention, Fig. 2 is a plan view showing a state in which a flat package IC is temporarily fixed to the printed circuit board of the same embodiment, and Fig. 3 is a plan view of a conventional printed circuit board. FIG. 4 is a plan view of the board, showing a state in which a flat package IC is temporarily fixed to a conventional printed board. 1: Land for solder reservoir, 3: Land group for IC terminal, 3a: Land for IC terminal, 4: Flat package IC, 5: IC terminal group, 5a: IC terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フラツトパツケージICの端子取出部に対応し
たIC端子用ランド群が設けられたプリント基板
において、前記IC端子用ランド群の内少なくと
も2ケ所のIC端子用ランドに対して前記各IC
端子用ランドと連続する半田溜用ランドを設けて
なることを特徴とするフラツトパツケージIC用
プリント基板。
In a printed circuit board provided with IC terminal land groups corresponding to the terminal extraction portions of a flat package IC, each of the IC
A printed circuit board for a flat package IC, characterized in that a land for a solder reservoir is provided which is continuous with a land for a terminal.
JP15837285U 1985-10-14 1985-10-14 Pending JPS6265876U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15837285U JPS6265876U (en) 1985-10-14 1985-10-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15837285U JPS6265876U (en) 1985-10-14 1985-10-14

Publications (1)

Publication Number Publication Date
JPS6265876U true JPS6265876U (en) 1987-04-23

Family

ID=31081797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15837285U Pending JPS6265876U (en) 1985-10-14 1985-10-14

Country Status (1)

Country Link
JP (1) JPS6265876U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009044737A1 (en) * 2007-10-01 2009-04-09 Murata Manufacturing Co., Ltd. Electronic component
CN110291628A (en) * 2017-02-22 2019-09-27 京瓷株式会社 Circuit board, electronic device and electronic module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009044737A1 (en) * 2007-10-01 2009-04-09 Murata Manufacturing Co., Ltd. Electronic component
CN110291628A (en) * 2017-02-22 2019-09-27 京瓷株式会社 Circuit board, electronic device and electronic module

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