JPS62196376U - - Google Patents
Info
- Publication number
- JPS62196376U JPS62196376U JP8490586U JP8490586U JPS62196376U JP S62196376 U JPS62196376 U JP S62196376U JP 8490586 U JP8490586 U JP 8490586U JP 8490586 U JP8490586 U JP 8490586U JP S62196376 U JPS62196376 U JP S62196376U
- Authority
- JP
- Japan
- Prior art keywords
- land group
- land
- attached
- terminal row
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図イ，ロは夫々本考案の一実施例における
プリント配線基板の平面図及びＡ―Ａ′断面図、
第２図イ，ロは夫々、巾狭ＩＣ使用時の平面図及
び側断面図、第３図イ，ロは夫々、巾広ＩＣ使用
時の平面図及び側断面図、第４図イ，ロは夫々、
形状の異なるＩＣの平面図、第５図イ，ロ及び第
６図は夫々、従来のプリント配線基板の平面図、
第７図イ，ロは従来例における巾狭ＩＣ使用時の
平面図及び側断面図、第８図イ，ロ，ハは夫々、
従来例における巾広ＩＣ使用時の平面図及び異な
る状態の側断面図である。
１，２…ＩＣ本体、３，３…端子、４…プリン
ト配線基板、５ａ，５ｂ，５ｃ，５ｄ…ランド、
７…半田レジスト。
Figures 1A and 1B are a plan view and a sectional view taken along A-A' of a printed wiring board according to an embodiment of the present invention, respectively;
Figures 2A and 2B are a plan view and side sectional view, respectively, when a narrow IC is used, Figure 3A, RO are a plan view and a side sectional view, respectively, when a wide IC is used, and Figure 4A, RO is a side sectional view, respectively. are respectively,
Plan views of ICs with different shapes, Figures 5A and 6, and Figure 6 are respectively plane views of conventional printed wiring boards.
Figures 7A and 7B are a plan view and a side sectional view when using a narrow IC in the conventional example, and Figure 8A, 2B, and 3C are respectively,
FIG. 2 is a plan view when a wide IC is used in a conventional example and a side sectional view in a different state. 1, 2... IC body, 3, 3... Terminal, 4... Printed wiring board, 5a, 5b, 5c, 5d... Land,
7...Solder resist.
Claims (1)
数種のフラツトパツクＩＣを共通にリフローハン
ダにより取付け可能であつて、前記ＩＣの一方の
端子列を取付ける第１のランド群と、他方の端子
列を取付ける第２のランド群とを備えるプリント
配線基板において、前記第２のランド群の各ラン
ドを半田レジストにより複数に分割してなるプリ
ント配線基板。 A plurality of types of flat pack ICs having the same pitch between terminals and different widths of the IC bodies can be commonly mounted by reflow soldering, and a first land group to which one terminal row of the IC is mounted is connected to a first land group to which the other terminal row is attached. A printed wiring board comprising a second land group to be attached, wherein each land of the second land group is divided into a plurality of parts by a solder resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8490586U JPS62196376U (en) | 1986-06-04 | 1986-06-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8490586U JPS62196376U (en) | 1986-06-04 | 1986-06-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62196376U true JPS62196376U (en) | 1987-12-14 |
Family
ID=30939820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8490586U Pending JPS62196376U (en) | 1986-06-04 | 1986-06-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62196376U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0224574U (en) * | 1988-07-30 | 1990-02-19 | ||
| JPH0224570U (en) * | 1988-07-30 | 1990-02-19 | ||
| JP2013153252A (en) * | 2012-01-24 | 2013-08-08 | Kyocera Crystal Device Corp | Piezoelectric device |
| JP2014517532A (en) * | 2011-06-06 | 2014-07-17 | インテル コーポレイション | Microelectronic substrates for selective packaging functions |
-
1986
- 1986-06-04 JP JP8490586U patent/JPS62196376U/ja active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0224574U (en) * | 1988-07-30 | 1990-02-19 | ||
| JPH0224570U (en) * | 1988-07-30 | 1990-02-19 | ||
| JP2014517532A (en) * | 2011-06-06 | 2014-07-17 | インテル コーポレイション | Microelectronic substrates for selective packaging functions |
| US9961769B2 (en) | 2011-06-06 | 2018-05-01 | Intel Corporation | Microelectronic substrate for alternate package functionality |
| JP2013153252A (en) * | 2012-01-24 | 2013-08-08 | Kyocera Crystal Device Corp | Piezoelectric device |