JPS6359376U - - Google Patents

Info

Publication number
JPS6359376U
JPS6359376U JP15413686U JP15413686U JPS6359376U JP S6359376 U JPS6359376 U JP S6359376U JP 15413686 U JP15413686 U JP 15413686U JP 15413686 U JP15413686 U JP 15413686U JP S6359376 U JPS6359376 U JP S6359376U
Authority
JP
Japan
Prior art keywords
land
electronic components
land portion
pattern
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15413686U
Other languages
Japanese (ja)
Other versions
JPH0744043Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986154136U priority Critical patent/JPH0744043Y2/en
Publication of JPS6359376U publication Critical patent/JPS6359376U/ja
Application granted granted Critical
Publication of JPH0744043Y2 publication Critical patent/JPH0744043Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案をフラツトパツケージＩＣの実
装に適用した場合の実施例を示す図、第２図はフ
ラツトパツケージＩＣの平面図、第３図は従来例
を示す図、第４図は従来例を説明するための説明
図、第５図は本考案をチツプ部品の実装に適用し
た場合の実施例を示す図、第６図は他の実施例を
示す図である。 １，２……フラツトパツケージＩＣ、３，８…
…ランドパターン、９，１６……第１ランド部、
１０，１７……第２ランド部、１１，１８……導
電パターン、１２，１３……チツプ部品。 FIG. 1 is a diagram showing an embodiment in which the present invention is applied to the mounting of a flat package IC, FIG. 2 is a plan view of the flat package IC, FIG. 3 is a diagram showing a conventional example, and FIG. FIG. 5 is an explanatory diagram for explaining a conventional example, FIG. 5 is a diagram showing an embodiment in which the present invention is applied to mounting chip components, and FIG. 6 is a diagram showing another embodiment. 1, 2...Flat package IC, 3, 8...
...Land pattern, 9,16...1st land part,
10, 17... Second land portion, 11, 18... Conductive pattern, 12, 13... Chip component.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 対向する端子間隔が異なる複数の電子部品に対
して兼用されるランドパターンとして、前記複数
の電子部品の各端子に対応する位置に各々ランド
部を形成し、同一端子側において近接する前記ラ
ンド部を、前記ランド部の幅より狭い導電パター
ンで接続して成ることを特徴としたプリント配線
板。 As a land pattern that is commonly used for a plurality of electronic components having different distances between opposing terminals, a land portion is formed at a position corresponding to each terminal of the plurality of electronic components, and the land portions adjacent to each other on the same terminal side are formed. , a printed wiring board characterized in that the connection is made by a conductive pattern narrower than the width of the land portion.
JP1986154136U 1986-10-07 1986-10-07 Printed wiring board Expired - Lifetime JPH0744043Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986154136U JPH0744043Y2 (en) 1986-10-07 1986-10-07 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986154136U JPH0744043Y2 (en) 1986-10-07 1986-10-07 Printed wiring board

Publications (2)

Publication Number Publication Date
JPS6359376U true JPS6359376U (en) 1988-04-20
JPH0744043Y2 JPH0744043Y2 (en) 1995-10-09

Family

ID=31073656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986154136U Expired - Lifetime JPH0744043Y2 (en) 1986-10-07 1986-10-07 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH0744043Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004612A (en) * 2007-06-22 2009-01-08 Nippon Seiki Co Ltd Printed wiring board
JP2016006702A (en) * 2014-06-20 2016-01-14 日東電工株式会社 Suspension substrate with circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621473U (en) * 1979-07-25 1981-02-25
JPS6153934U (en) * 1984-09-11 1986-04-11

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621473U (en) * 1979-07-25 1981-02-25
JPS6153934U (en) * 1984-09-11 1986-04-11

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004612A (en) * 2007-06-22 2009-01-08 Nippon Seiki Co Ltd Printed wiring board
JP2016006702A (en) * 2014-06-20 2016-01-14 日東電工株式会社 Suspension substrate with circuit

Also Published As

Publication number Publication date
JPH0744043Y2 (en) 1995-10-09

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