JPH0351860U - - Google Patents
Info
- Publication number
- JPH0351860U JPH0351860U JP11365089U JP11365089U JPH0351860U JP H0351860 U JPH0351860 U JP H0351860U JP 11365089 U JP11365089 U JP 11365089U JP 11365089 U JP11365089 U JP 11365089U JP H0351860 U JPH0351860 U JP H0351860U
- Authority
- JP
- Japan
- Prior art keywords
- view
- showing
- hybrid
- perspective
- center
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
第１図は本考案の第１の実施例に係るハイブリ
ツドＩＣを示す斜視図、第２図はその端子部を示
す一部拡大断面図、第３図は本考案の第２の実施
例に係るハイブリツドＩＣを示す斜視図、第４図
はその端子部を示す一部拡大断面図、第５図は従
来のハイブリツドＩＣの１例を示す斜視図、第６
図はその端子部を示す一部拡大断面図、第７図は
その平面図である。
１，１１……基板、２，１２……リード端子、
３，１３……半田付けランド、４，１４……導体
配線、５，１５……回路素子、６，６ａ，１６…
…半田、７……端子、８……プリント基板、９…
…銅パターン、１０，１７……ボンデイングワイ
ヤ。
Fig. 1 is a perspective view showing a hybrid IC according to a first embodiment of the present invention, Fig. 2 is a partially enlarged sectional view showing the terminal portion thereof, and Fig. 3 is a perspective view showing a hybrid IC according to a second embodiment of the present invention. FIG. 4 is a partially enlarged cross-sectional view showing a terminal portion thereof; FIG. 5 is a perspective view showing an example of a conventional hybrid IC; FIG. 6 is a perspective view showing a hybrid IC.
The figure is a partially enlarged sectional view showing the terminal portion, and FIG. 7 is a plan view thereof. 1, 11... Board, 2, 12... Lead terminal,
3, 13... Soldering land, 4, 14... Conductor wiring, 5, 15... Circuit element, 6, 6a, 16...
...Solder, 7...Terminal, 8...Printed circuit board, 9...
...Copper pattern, 10,17...Bonding wire.
Claims (1)
記端部に配置された端子とを有することを特徴と
するハイブリツドＩＣ。 A hybrid IC characterized by having a substrate whose ends are bent relative to the center, and terminals arranged at the ends.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11365089U JPH0351860U (en) | 1989-09-28 | 1989-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11365089U JPH0351860U (en) | 1989-09-28 | 1989-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0351860U true JPH0351860U (en) | 1991-05-20 |
Family
ID=31662057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11365089U Pending JPH0351860U (en) | 1989-09-28 | 1989-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0351860U (en) |
-
1989
- 1989-09-28 JP JP11365089U patent/JPH0351860U/ja active Pending
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