JPS6247171U - - Google Patents

Info

Publication number
JPS6247171U
JPS6247171U JP13902985U JP13902985U JPS6247171U JP S6247171 U JPS6247171 U JP S6247171U JP 13902985 U JP13902985 U JP 13902985U JP 13902985 U JP13902985 U JP 13902985U JP S6247171 U JPS6247171 U JP S6247171U
Authority
JP
Japan
Prior art keywords
pads
view
integrated circuit
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13902985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13902985U priority Critical patent/JPS6247171U/ja
Publication of JPS6247171U publication Critical patent/JPS6247171U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本考案の実施例のプリント基板を示
す平面図、第1図b,cは第1図aのプリント基
板に集積回路を接続した状態を示す平面図および
その側面図、第1図d,eは第1図bの接続部分
を詳細に示す平面図およびその側面図、第2図a
は従来のプリント基板のパツドを示す平面図、第
2図b,cは第2図aのプリント板に集積回路を
接続した状態を示す平面図、およびその側面図、
第2図d,eは第2図bの接続部分を詳細に示す
平面図およびその側面図である。 10……プリント基板、11……集積回路実装
用パツド、20……フラツト・パツケージ型集積
回路、21……集積回路リード、30……半田、
40……オームメータ。
1a is a plan view showing a printed circuit board according to an embodiment of the present invention; FIGS. 1b and 1c are a plan view and a side view of the printed circuit board shown in FIG. Figures d and e are a plan view and side view showing the connection part in Figure 1 b in detail, and Figure 2 a.
2 is a plan view showing a pad of a conventional printed circuit board, FIGS. 2b and 2c are plan views showing a state in which an integrated circuit is connected to the printed board of FIG. 2a, and a side view thereof,
FIGS. 2d and 2e are a plan view and a side view showing the connecting portion of FIG. 2b in detail. 10... Printed circuit board, 11... Integrated circuit mounting pad, 20... Flat package integrated circuit, 21... Integrated circuit lead, 30... Solder,
40...Ohmmeter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フラツト・パツケージ型集積回路の複数のリー
ドとそれぞれ電気的に接続されるパツドを有する
プリント基板において、前記パツドの各々が2つ
の長方形のパツドにより構成されていることを特
徴とするプリント基板。
1. A printed circuit board having pads each electrically connected to a plurality of leads of a flat package integrated circuit, wherein each of the pads is constituted by two rectangular pads.
JP13902985U 1985-09-10 1985-09-10 Pending JPS6247171U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13902985U JPS6247171U (en) 1985-09-10 1985-09-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13902985U JPS6247171U (en) 1985-09-10 1985-09-10

Publications (1)

Publication Number Publication Date
JPS6247171U true JPS6247171U (en) 1987-03-23

Family

ID=31044552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13902985U Pending JPS6247171U (en) 1985-09-10 1985-09-10

Country Status (1)

Country Link
JP (1) JPS6247171U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205498A (en) * 1988-02-10 1989-08-17 Toyo Commun Equip Co Ltd Printed wiring pattern and detecting method for non-soldering

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205498A (en) * 1988-02-10 1989-08-17 Toyo Commun Equip Co Ltd Printed wiring pattern and detecting method for non-soldering

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