JPS61127670U - - Google Patents
Info
- Publication number
- JPS61127670U JPS61127670U JP1038985U JP1038985U JPS61127670U JP S61127670 U JPS61127670 U JP S61127670U JP 1038985 U JP1038985 U JP 1038985U JP 1038985 U JP1038985 U JP 1038985U JP S61127670 U JPS61127670 U JP S61127670U
- Authority
- JP
- Japan
- Prior art keywords
- flat package
- pins
- connection device
- area
- pattern corresponding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図及び第２図はそれぞれこの考案に係るフ
ラツトパツケージＩＣの接続装置の一実施例を示
す平面図及び側面図、第３図は同実施例の変形例
を示す平面図、第４図及び第５図はそれぞれ従来
のフラツトパツケージＩＣの接続手段を示す平面
図及び側面図である。
１１……フラツトパツケージＩＣ、１２……印
刷配線板、１３……半田、１１ａ〜１１ｈ……ピ
ン、１２ａ〜１２ｈ……電極パターン。
1 and 2 are a plan view and a side view, respectively, showing an embodiment of a connection device for a flat package IC according to this invention, FIG. 3 is a plan view showing a modification of the same embodiment, and FIG. 4 and FIG. 5 are a plan view and a side view, respectively, showing connection means of a conventional flat package IC. DESCRIPTION OF SYMBOLS 11... Flat package IC, 12... Printed wiring board, 13... Solder, 11a-11h... Pin, 12a-12h... Electrode pattern.
Claims (1)
数のピンそれぞれに対応して印刷配線板に形成さ
れた複数の電極パターンに半田付けするフラツト
パツケージＩＣの接続装置において、前記複数の
電極パターンのうち、前記フラツトパツケージＩ
Ｃの端部に位置するピンに対応する電極パターン
の面積を、他のピンに対応する電極パターンの面
積よりも広くするようにしてなることを特徴とす
るフラツトパツケージＩＣの接続装置。 In a flat package IC connection device for soldering a plurality of pins of a flat package IC to a plurality of electrode patterns formed on a printed wiring board corresponding to each of the plurality of pins, one of the plurality of electrode patterns , the flat package I
1. A connection device for a flat package IC, characterized in that the area of the electrode pattern corresponding to the pin located at the end of the IC is made larger than the area of the electrode pattern corresponding to the other pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1038985U JPS61127670U (en) | 1985-01-28 | 1985-01-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1038985U JPS61127670U (en) | 1985-01-28 | 1985-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61127670U true JPS61127670U (en) | 1986-08-11 |
Family
ID=30491527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1038985U Pending JPS61127670U (en) | 1985-01-28 | 1985-01-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127670U (en) |
-
1985
- 1985-01-28 JP JP1038985U patent/JPS61127670U/ja active Pending