JPS6320472U - - Google Patents
Info
- Publication number
- JPS6320472U JPS6320472U JP11419686U JP11419686U JPS6320472U JP S6320472 U JPS6320472 U JP S6320472U JP 11419686 U JP11419686 U JP 11419686U JP 11419686 U JP11419686 U JP 11419686U JP S6320472 U JPS6320472 U JP S6320472U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- integrated circuit
- flat pack
- pack type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図乃至第３図は本考案に係るプリント配線
板の要部の一実施例を示したもので、第１図はそ
のプリント配線板とフラツトパツク形集積回路の
半田付け前を示した斜視図、第２図および第３図
はそのプリント配線板にフラツトパツク形集積回
路を半田付けした状態を示した平面図、第４図は
本考案に係るプリント配線板の要部の他の実施例
を示したもので、そのプリント配線板にフラツト
パツク形集積回路を半田付けした状態を示した平
面図、第５図は本考案に係るプリント配線板の要
部のさらに他の実施例を示したもので、そのプリ
ント配線板にフラツトパツク形集積回路を半田付
けした状態を示した平面図、第６図および第７図
は従来のプリント配線板を示したもので、そのプ
リント配線板にフラツトパツク形集積回路を半田
付けした状態をそれぞれ示した平面図である。
１……フラツトパツク形集積回路、１ａ……リ
ード電極、１１，２１，３１……プリント配線板
、１２，２２，３２……導体パターン、１２ａ，
２２ａ，３２ａ……ランド、１３，２３，３３…
…半田フエレツト。
1 to 3 show an embodiment of the main parts of the printed wiring board according to the present invention, and FIG. 1 is a perspective view showing the printed wiring board and the flat pack integrated circuit before soldering. , FIGS. 2 and 3 are plan views showing flat pack integrated circuits soldered to the printed wiring board, and FIG. 4 shows another embodiment of the main parts of the printed wiring board according to the present invention. 5 is a plan view showing a state in which a flat pack type integrated circuit is soldered to the printed wiring board, and FIG. 5 shows still another embodiment of the main part of the printed wiring board according to the present invention. 6 and 7 are plan views showing a state in which a flat pack type integrated circuit is soldered to the printed wiring board, and Figures 6 and 7 show a conventional printed wiring board, and a flat pack type integrated circuit is soldered to the printed wiring board. FIG. 4 is a plan view showing the attached state. DESCRIPTION OF SYMBOLS 1... Flat pack integrated circuit, 1a... Lead electrode, 11, 21, 31... Printed wiring board, 12, 22, 32... Conductor pattern, 12a,
22a, 32a... land, 13, 23, 33...
…Handa Fellets.
Claims (1)
配線板において、前記フラツトパツク形集積回路
のリード電極を接続するために並設される複数の
ランドを、それぞれ同一形状かつ非直線的に形成
したことを特徴とするプリント配線板。 A printed wiring board on which a flat pack type integrated circuit is mounted, characterized in that a plurality of lands arranged in parallel for connecting lead electrodes of the flat pack type integrated circuit are each formed in the same shape and non-linearly. wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11419686U JPS6320472U (en) | 1986-07-25 | 1986-07-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11419686U JPS6320472U (en) | 1986-07-25 | 1986-07-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320472U true JPS6320472U (en) | 1988-02-10 |
Family
ID=30996709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11419686U Pending JPS6320472U (en) | 1986-07-25 | 1986-07-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320472U (en) |
-
1986
- 1986-07-25 JP JP11419686U patent/JPS6320472U/ja active Pending