JPH0426520U - - Google Patents
Info
- Publication number
- JPH0426520U JPH0426520U JP6785990U JP6785990U JPH0426520U JP H0426520 U JPH0426520 U JP H0426520U JP 6785990 U JP6785990 U JP 6785990U JP 6785990 U JP6785990 U JP 6785990U JP H0426520 U JPH0426520 U JP H0426520U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- mount chip
- electrodes
- mirror
- finished
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第1図は本考案の実施例を示す表面実装用チツ
プ部品の実装状態を示す断面図、第2図は従来の
チツプ部品の電極構造を示す断面図、第3図は従
来の他の表面実装用チツプ部品の電極構造を示す
断面図、第4図は従来の問題点の説明図、第5図
は本考案の他の実施例を示す表面実装用チツプ部
品の実装状態を示す断面図である。
20……基板、21,22……パツド、23,
32……第1の電極、24,35……第2の電極
、25,31……表面実装用チツプ部品、33…
…Ag−Pd層、34……Auメツキ。
Fig. 1 is a sectional view showing the mounting state of a surface mount chip component according to an embodiment of the present invention, Fig. 2 is a sectional view showing the electrode structure of a conventional chip part, and Fig. 3 is a sectional view of another conventional surface mount chip component. FIG. 4 is an explanatory diagram of conventional problems, and FIG. 5 is a cross-sectional view showing the mounting state of a surface mount chip component showing another embodiment of the present invention. . 20... Board, 21, 22... Pad, 23,
32...First electrode, 24,35...Second electrode, 25,31...Surface mounting chip component, 33...
...Ag-Pd layer, 34...Au plating.
Claims (1)
部品において、 (a) 鏡面仕上げを行わない表面を有する第1
の電極と、 (b) 鏡面仕上げを行つた表面を有する第2の
電極とを具備する表面実装用チツプ部品。 (2) 両側に電極が形成される表面実装用チツプ
部品において、 (a) メツキを施さない表面を有する第1の電
極と、 (b) Auメツキを施した表面を有する第2の
電極とを具備する表面実装用チツプ部品。 (3) 両側に電極が形成される表面実装用チツプ
部品の実装構造において、 (a) 鏡面仕上げを行わない表面を有する第1
の電極と、 (b) 鏡面仕上げを行つた表面を有する第2の
電極とを設け、 (c) 前記第1の電極をリフロー時に先行して
加熱される側の基板パツドに、前記第2の電極を
リフロー時に遅れて加熱される側の基板のパツド
にそれぞれ接続してなる表面実装用チツプ部品の
実装構造。 (4) 両側に電極が形成される表面実装用チツプ
部品の実装構造において、 (a) メツキを施さない表面を有する第1の電
極と、 (b) Auメツキを施した表面を有する第2の
電極とを設け、 (c) 前記第1の電極をリフロー時に先行して
加熱される側の基板パツドに、前記第2の電極を
リフロー時に遅れて加熱される側の基板のパツド
にそれぞれ接続してなる表面実装用チツプ部品の
実装構造。[Claims for Utility Model Registration] (1) In a surface mount chip component in which electrodes are formed on both sides, (a) a first component having a surface that is not mirror-finished;
and (b) a second electrode having a mirror-finished surface. (2) In a surface mount chip component in which electrodes are formed on both sides, (a) a first electrode having an unplated surface, and (b) a second electrode having an Au-plated surface. Includes surface mount chip parts. (3) In the mounting structure of a surface mount chip component in which electrodes are formed on both sides, (a) the first part has a surface that is not mirror-finished;
(b) a second electrode having a mirror-finished surface; (c) the first electrode is placed on a substrate pad on the side that is heated in advance during reflow; A mounting structure for surface mount chip components in which electrodes are connected to pads on the board that are heated later during reflow. (4) In the mounting structure of a surface-mount chip component in which electrodes are formed on both sides, (a) a first electrode having an unplated surface, and (b) a second electrode having an Au-plated surface. (c) connecting the first electrode to a pad of the substrate that is heated earlier during reflow, and connecting the second electrode to a pad of the substrate that is heated later during reflow; Mounting structure for surface mount chip components.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6785990U JPH0426520U (en) | 1990-06-28 | 1990-06-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6785990U JPH0426520U (en) | 1990-06-28 | 1990-06-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0426520U true JPH0426520U (en) | 1992-03-03 |
Family
ID=31601809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6785990U Pending JPH0426520U (en) | 1990-06-28 | 1990-06-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0426520U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012212794A (en) * | 2011-03-31 | 2012-11-01 | Stanley Electric Co Ltd | Side emitting and receiving optical semiconductor device for surface mounting and module using the same |
-
1990
- 1990-06-28 JP JP6785990U patent/JPH0426520U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012212794A (en) * | 2011-03-31 | 2012-11-01 | Stanley Electric Co Ltd | Side emitting and receiving optical semiconductor device for surface mounting and module using the same |