JPH0388350U - - Google Patents

Info

Publication number
JPH0388350U
JPH0388350U JP1989150344U JP15034489U JPH0388350U JP H0388350 U JPH0388350 U JP H0388350U JP 1989150344 U JP1989150344 U JP 1989150344U JP 15034489 U JP15034489 U JP 15034489U JP H0388350 U JPH0388350 U JP H0388350U
Authority
JP
Japan
Prior art keywords
tab tape
semiconductor chip
semiconductor device
bonded
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989150344U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989150344U priority Critical patent/JPH0388350U/ja
Priority to KR2019900019502U priority patent/KR930003872Y1/en
Publication of JPH0388350U publication Critical patent/JPH0388350U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る半導体装置の一実施例を
示す断面図、第2〜3図は他の実施例を示す要部
断面図、第4図は半導体装置の他の実施例を示す
断面図、第5図は従来の半導体装置を示す断面図
を各々示す。 図において、10……半導体チツプ、12……
TAB用テープ、14……封止樹脂、15……ベ
ースフイルム、16……導体パターン、18……
インナーリード、20……バンプ、22……アウ
ターリード、24……リードフレーム、30……
放熱板、32……接着剤。
FIG. 1 is a sectional view showing one embodiment of the semiconductor device according to the present invention, FIGS. 2 and 3 are sectional views of main parts showing other embodiments, and FIG. 4 is a sectional view showing another embodiment of the semiconductor device. 5 and 5 each show a cross-sectional view of a conventional semiconductor device. In the figure, 10...semiconductor chip, 12...
TAB tape, 14... Sealing resin, 15... Base film, 16... Conductor pattern, 18...
Inner lead, 20... bump, 22... outer lead, 24... lead frame, 30...
Heat sink, 32...Adhesive.

Claims (1)

【実用新案登録請求の範囲】 1 TAB用テープに半導体チツプが搭載されて
いると共に、前記TAB用テープと半導体チツプ
とがバンプを介して一括ボンデイングされ、且つ
樹脂封止されている半導体装置において、 該半導体チツプに接合され又は半導体チツプの
近傍に設けられている放熱板上に、TAB用テー
プを構成するベースフイルムの少なくとも一部が
接合されていることを特徴とする半導体装置。 2 TAB用テープのグランド線路と放熱板とが
電気的に接続されている請求項第1項記載の半導
体装置。
[Claims for Utility Model Registration] 1. A semiconductor device in which a semiconductor chip is mounted on a TAB tape, and the TAB tape and the semiconductor chip are collectively bonded via bumps and sealed with resin, A semiconductor device characterized in that at least a part of a base film constituting a TAB tape is bonded to a heat sink bonded to the semiconductor chip or provided in the vicinity of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the ground line of the TAB tape and the heat sink are electrically connected.
JP1989150344U 1989-12-26 1989-12-26 Pending JPH0388350U (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1989150344U JPH0388350U (en) 1989-12-26 1989-12-26
KR2019900019502U KR930003872Y1 (en) 1989-12-26 1990-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989150344U JPH0388350U (en) 1989-12-26 1989-12-26

Publications (1)

Publication Number Publication Date
JPH0388350U true JPH0388350U (en) 1991-09-10

Family

ID=15494942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989150344U Pending JPH0388350U (en) 1989-12-26 1989-12-26

Country Status (2)

Country Link
JP (1) JPH0388350U (en)
KR (1) KR930003872Y1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101301782B1 (en) * 2011-03-30 2013-08-29 앰코 테크놀로지 코리아 주식회사 Semiconductor package and fabricating method of thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5243364A (en) * 1975-10-01 1977-04-05 Hitachi Ltd Power semiconductor device and process for production of same
JPH01304738A (en) * 1988-06-01 1989-12-08 Mitsubishi Electric Corp Semiconductor device package structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5243364A (en) * 1975-10-01 1977-04-05 Hitachi Ltd Power semiconductor device and process for production of same
JPH01304738A (en) * 1988-06-01 1989-12-08 Mitsubishi Electric Corp Semiconductor device package structure

Also Published As

Publication number Publication date
KR910013038U (en) 1991-07-30
KR930003872Y1 (en) 1993-06-23

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