JPH0388350U - - Google Patents
Info
- Publication number
- JPH0388350U JPH0388350U JP1989150344U JP15034489U JPH0388350U JP H0388350 U JPH0388350 U JP H0388350U JP 1989150344 U JP1989150344 U JP 1989150344U JP 15034489 U JP15034489 U JP 15034489U JP H0388350 U JPH0388350 U JP H0388350U
- Authority
- JP
- Japan
- Prior art keywords
- tab tape
- semiconductor chip
- semiconductor device
- bonded
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案に係る半導体装置の一実施例を
示す断面図、第2〜3図は他の実施例を示す要部
断面図、第4図は半導体装置の他の実施例を示す
断面図、第5図は従来の半導体装置を示す断面図
を各々示す。
図において、10……半導体チツプ、12……
TAB用テープ、14……封止樹脂、15……ベ
ースフイルム、16……導体パターン、18……
インナーリード、20……バンプ、22……アウ
ターリード、24……リードフレーム、30……
放熱板、32……接着剤。
FIG. 1 is a sectional view showing one embodiment of the semiconductor device according to the present invention, FIGS. 2 and 3 are sectional views of main parts showing other embodiments, and FIG. 4 is a sectional view showing another embodiment of the semiconductor device. 5 and 5 each show a cross-sectional view of a conventional semiconductor device. In the figure, 10...semiconductor chip, 12...
TAB tape, 14... Sealing resin, 15... Base film, 16... Conductor pattern, 18...
Inner lead, 20... bump, 22... outer lead, 24... lead frame, 30...
Heat sink, 32...Adhesive.
Claims (1)
いると共に、前記TAB用テープと半導体チツプ
とがバンプを介して一括ボンデイングされ、且つ
樹脂封止されている半導体装置において、 該半導体チツプに接合され又は半導体チツプの
近傍に設けられている放熱板上に、TAB用テー
プを構成するベースフイルムの少なくとも一部が
接合されていることを特徴とする半導体装置。 2 TAB用テープのグランド線路と放熱板とが
電気的に接続されている請求項第1項記載の半導
体装置。[Claims for Utility Model Registration] 1. A semiconductor device in which a semiconductor chip is mounted on a TAB tape, and the TAB tape and the semiconductor chip are collectively bonded via bumps and sealed with resin, A semiconductor device characterized in that at least a part of a base film constituting a TAB tape is bonded to a heat sink bonded to the semiconductor chip or provided in the vicinity of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the ground line of the TAB tape and the heat sink are electrically connected.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989150344U JPH0388350U (en) | 1989-12-26 | 1989-12-26 | |
KR2019900019502U KR930003872Y1 (en) | 1989-12-26 | 1990-12-11 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989150344U JPH0388350U (en) | 1989-12-26 | 1989-12-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0388350U true JPH0388350U (en) | 1991-09-10 |
Family
ID=15494942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989150344U Pending JPH0388350U (en) | 1989-12-26 | 1989-12-26 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH0388350U (en) |
KR (1) | KR930003872Y1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101301782B1 (en) * | 2011-03-30 | 2013-08-29 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method of thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5243364A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Power semiconductor device and process for production of same |
JPH01304738A (en) * | 1988-06-01 | 1989-12-08 | Mitsubishi Electric Corp | Semiconductor device package structure |
-
1989
- 1989-12-26 JP JP1989150344U patent/JPH0388350U/ja active Pending
-
1990
- 1990-12-11 KR KR2019900019502U patent/KR930003872Y1/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5243364A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Power semiconductor device and process for production of same |
JPH01304738A (en) * | 1988-06-01 | 1989-12-08 | Mitsubishi Electric Corp | Semiconductor device package structure |
Also Published As
Publication number | Publication date |
---|---|
KR910013038U (en) | 1991-07-30 |
KR930003872Y1 (en) | 1993-06-23 |