JPH0338633U - - Google Patents
Info
- Publication number
- JPH0338633U JPH0338633U JP1989098578U JP9857889U JPH0338633U JP H0338633 U JPH0338633 U JP H0338633U JP 1989098578 U JP1989098578 U JP 1989098578U JP 9857889 U JP9857889 U JP 9857889U JP H0338633 U JPH0338633 U JP H0338633U
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- semiconductor bare
- semiconductor
- glass dam
- outer periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す平面構造図、第
２図は第１図のＡＡ′断面図である。
図に於いて１…基板、２…導体パターン、３…
半導体ベアチツプ、４…ランド部分、５…半田バ
ンプ、６…ガラスダムである。
FIG. 1 is a plan structural view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA' in FIG. In the figure, 1...board, 2...conductor pattern, 3...
Semiconductor bare chip, 4...land portion, 5...solder bump, 6...glass dam.
Claims (1)
プを搭載し、かつ前記半導体ベアチツプの外周の
一部又は全部にガラスダムを設け、前記導体パタ
ーンと前記半導体ベアチツプを半田バンプを溶融
して接続して成る半導体装置に於いて、前記ガラ
スダムの内側エツジを前記半導体ベアチツプ外形
寸法より０．０５〜０．３mm大きくし、かつ前記
ガラスダムが前記半導体ベアチツプの外周の導体
パターン部分を断続的に取り囲んだ事を特徴とす
る半導体装置。 A semiconductor device comprising a semiconductor bare chip mounted on a substrate having a conductive pattern, a glass dam provided on a part or all of the outer periphery of the semiconductor bare chip, and the conductive pattern and the semiconductor bare chip connected by melting solder bumps. A semiconductor characterized in that the inner edge of the glass dam is 0.05 to 0.3 mm larger than the outer dimension of the semiconductor bare chip, and the glass dam intermittently surrounds a conductor pattern portion on the outer periphery of the semiconductor bare chip. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989098578U JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989098578U JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338633U true JPH0338633U (en) | 1991-04-15 |
Family
ID=31647665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989098578U Pending JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338633U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347238A (en) * | 2018-04-03 | 2019-10-18 | 富士通电子零件有限公司 | Input equipment |
-
1989
- 1989-08-24 JP JP1989098578U patent/JPH0338633U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347238A (en) * | 2018-04-03 | 2019-10-18 | 富士通电子零件有限公司 | Input equipment |