JPH0359639U - - Google Patents
Info
- Publication number
- JPH0359639U JPH0359639U JP1989119150U JP11915089U JPH0359639U JP H0359639 U JPH0359639 U JP H0359639U JP 1989119150 U JP1989119150 U JP 1989119150U JP 11915089 U JP11915089 U JP 11915089U JP H0359639 U JPH0359639 U JP H0359639U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- semiconductor
- plated
- mounting
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
第１図は本考案による半導体搭載用基板の一実
施例を示す上面図で、第２図は本考案にて作成し
た基板に半導体チツプを搭載し樹脂封止したもの
の側面の断面図である。また、第３図は従来の半
導体搭載用基板の概念を示す上面図で、第４図は
従来の半導体搭載用基板に半導体チツプを搭載し
樹脂封止したものの側面の断面図である。
FIG. 1 is a top view showing an embodiment of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a side sectional view of the substrate prepared according to the present invention with a semiconductor chip mounted thereon and sealed with resin. Further, FIG. 3 is a top view showing the concept of a conventional semiconductor mounting substrate, and FIG. 4 is a side sectional view of a conventional semiconductor mounting substrate with a semiconductor chip mounted thereon and sealed with resin.
Claims (1)
チツプを搭載した後、凹部周辺のボンデイングパ
ツドを取り囲む位置に樹脂枠を貼り付けて封止樹
脂を注入する半導体搭載用基板において、前記樹
脂枠の下部およびその内側に位置する回路パター
ン部分には、厚さ５〜１５μｍのニツケルメツキ
を施し、さらに金メツキを施したことを特徴とす
る半導体搭載用基板。 In a semiconductor mounting board in which a recess is provided in a printed circuit board, a semiconductor chip is mounted in the recess, a resin frame is attached to a position surrounding a bonding pad around the recess, and a sealing resin is injected. A substrate for mounting a semiconductor, characterized in that the lower part and the circuit pattern portion located inside thereof are plated with nickel to a thickness of 5 to 15 μm, and further plated with gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989119150U JP2505359Y2 (en) | 1989-10-13 | 1989-10-13 | Semiconductor mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989119150U JP2505359Y2 (en) | 1989-10-13 | 1989-10-13 | Semiconductor mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0359639U true JPH0359639U (en) | 1991-06-12 |
| JP2505359Y2 JP2505359Y2 (en) | 1996-07-31 |
Family
ID=31667288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989119150U Expired - Lifetime JP2505359Y2 (en) | 1989-10-13 | 1989-10-13 | Semiconductor mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2505359Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009234197A (en) * | 2008-03-28 | 2009-10-15 | Toppan Printing Co Ltd | Sticking apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148480A (en) * | 1978-05-15 | 1979-11-20 | Nec Corp | Semiconductor device |
| JPS62163347A (en) * | 1986-01-13 | 1987-07-20 | Ibiden Co Ltd | Substrate for mounting electronic part |
-
1989
- 1989-10-13 JP JP1989119150U patent/JP2505359Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148480A (en) * | 1978-05-15 | 1979-11-20 | Nec Corp | Semiconductor device |
| JPS62163347A (en) * | 1986-01-13 | 1987-07-20 | Ibiden Co Ltd | Substrate for mounting electronic part |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009234197A (en) * | 2008-03-28 | 2009-10-15 | Toppan Printing Co Ltd | Sticking apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2505359Y2 (en) | 1996-07-31 |