JPH0363948U - - Google Patents
Info
- Publication number
- JPH0363948U JPH0363948U JP12363589U JP12363589U JPH0363948U JP H0363948 U JPH0363948 U JP H0363948U JP 12363589 U JP12363589 U JP 12363589U JP 12363589 U JP12363589 U JP 12363589U JP H0363948 U JPH0363948 U JP H0363948U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- circuit pattern
- sealing resin
- area
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 3
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案による半導体搭載用基板の一実
施例を示す上面図で、第２図は本考案にて作成し
た基板に半導体チツプを搭載し樹脂封止したもの
の側面の断面図である。また、第３図は従来の半
導体搭載用基板の概念を示す上面図であり、第４
図は従来の半導体搭載用基板に半導体チツプを搭
載し樹脂封止したものの側面の断面図である。
FIG. 1 is a top view showing an embodiment of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a side sectional view of the substrate prepared according to the present invention with a semiconductor chip mounted thereon and sealed with resin. FIG. 3 is a top view showing the concept of a conventional semiconductor mounting board;
The figure is a side sectional view of a conventional semiconductor mounting substrate on which a semiconductor chip is mounted and sealed with resin.
Claims (1)
チツプを搭載した後、凹部周辺のボンデイングパ
ツドを取り囲む位置に樹脂枠を貼り付けて封止樹
脂を注入する半導体搭載用基板において、前記樹
脂枠および封止樹脂で覆われる部位における全面
積に対する回路パターン部の面積の割合を５０〜
８０％の範囲とし、さらに該回路パターン部には
金メツキを施したことを特徴とする半導体搭載用
基板。 A semiconductor mounting board in which a recess is provided in a printed circuit board, a semiconductor chip is mounted in the recess, a resin frame is attached to a position surrounding a bonding pad around the recess, and a sealing resin is injected. The ratio of the area of the circuit pattern part to the total area of the part covered with the sealing resin is 50~
80% range, and the circuit pattern portion is further plated with gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12363589U JPH0363948U (en) | 1989-10-24 | 1989-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12363589U JPH0363948U (en) | 1989-10-24 | 1989-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0363948U true JPH0363948U (en) | 1991-06-21 |
Family
ID=31671601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12363589U Pending JPH0363948U (en) | 1989-10-24 | 1989-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0363948U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61258457A (en) * | 1985-05-13 | 1986-11-15 | Nec Corp | Resin sealed type semiconductor device |
-
1989
- 1989-10-24 JP JP12363589U patent/JPH0363948U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61258457A (en) * | 1985-05-13 | 1986-11-15 | Nec Corp | Resin sealed type semiconductor device |