JPH0292936U - - Google Patents
Info
- Publication number
- JPH0292936U JPH0292936U JP1989000960U JP96089U JPH0292936U JP H0292936 U JPH0292936 U JP H0292936U JP 1989000960 U JP1989000960 U JP 1989000960U JP 96089 U JP96089 U JP 96089U JP H0292936 U JPH0292936 U JP H0292936U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- printed circuit
- chip carrier
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
第１図は、本考案に於けるチツプキヤリアＩＣ
の実施例を示す平面図。第２図は、第１図の側面
図である。第３図は、本考案に於けるチツプキヤ
リアＩＣの他の実施例を示す平面図。第４図は、
第３図の側面図である。第５図は、従来のチツプ
キヤリアＩＣの平面図。
１……プリント基板、２……外部接続用凸起端
子、３……外部接続用端子。
Figure 1 shows the chip carrier IC in this invention.
FIG. FIG. 2 is a side view of FIG. 1. FIG. 3 is a plan view showing another embodiment of the chip carrier IC according to the present invention. Figure 4 shows
FIG. 4 is a side view of FIG. 3; FIG. 5 is a plan view of a conventional chip carrier IC. 1... Printed circuit board, 2... Convex terminal for external connection, 3... Terminal for external connection.
Claims (1)
ト基板の配線パターンと該ＩＣチツプを接続し、
樹脂で封止を行なつたチツプキヤリアＩＣに於い
て、該チツプキヤリアＩＣの外部接続端子が、凸
起状に形成されていることを特徴とするチツプキ
ヤリアＩＣ。 Fixing an IC chip to a printed circuit board, connecting the wiring pattern of the printed circuit board and the IC chip,
A chip carrier IC sealed with a resin, wherein an external connection terminal of the chip carrier IC is formed in a convex shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989000960U JPH0292936U (en) | 1989-01-09 | 1989-01-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989000960U JPH0292936U (en) | 1989-01-09 | 1989-01-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0292936U true JPH0292936U (en) | 1990-07-24 |
Family
ID=31200434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989000960U Pending JPH0292936U (en) | 1989-01-09 | 1989-01-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0292936U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4941901A (en) * | 1972-08-29 | 1974-04-19 | ||
| JPS4942624A (en) * | 1972-08-23 | 1974-04-22 | ||
| JPH01235356A (en) * | 1988-03-16 | 1989-09-20 | Nec Corp | Module board |
-
1989
- 1989-01-09 JP JP1989000960U patent/JPH0292936U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4942624A (en) * | 1972-08-23 | 1974-04-22 | ||
| JPS4941901A (en) * | 1972-08-29 | 1974-04-19 | ||
| JPH01235356A (en) * | 1988-03-16 | 1989-09-20 | Nec Corp | Module board |