JPS6196558U - - Google Patents

Info

Publication number
JPS6196558U
JPS6196558U JP1984181203U JP18120384U JPS6196558U JP S6196558 U JPS6196558 U JP S6196558U JP 1984181203 U JP1984181203 U JP 1984181203U JP 18120384 U JP18120384 U JP 18120384U JP S6196558 U JPS6196558 U JP S6196558U
Authority
JP
Japan
Prior art keywords
chips
hybrid integrated
integrated circuit
epoxy resin
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984181203U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984181203U priority Critical patent/JPS6196558U/ja
Publication of JPS6196558U publication Critical patent/JPS6196558U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の混成集積回路の平面図、第２
図は第１図のＡ−Ａ′線断面図、第３図は従来の
混成集積回路の断面図である。 １…本考案による基板、２…コーテイング樹脂
、３…ＩＣチツプ、４…ＩＣチツプ、５…コーテ
イング樹脂、６…従来の基板。 Figure 1 is a plan view of the hybrid integrated circuit of the present invention;
The figure is a sectional view taken along the line A-A' in FIG. 1, and FIG. 3 is a sectional view of a conventional hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Substrate according to the present invention, 2... Coating resin, 3... IC chip, 4... IC chip, 5... Coating resin, 6... Conventional board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＩＣチツプを搭載する混成集積回路において、
ＩＣチツプをエポキシ系樹脂を介して同一位置に
搭載する、２段構造を有する混成集積回路。 In hybrid integrated circuits equipped with IC chips,
A hybrid integrated circuit with a two-stage structure in which IC chips are mounted in the same position via epoxy resin.
JP1984181203U 1984-11-29 1984-11-29 Pending JPS6196558U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984181203U JPS6196558U (en) 1984-11-29 1984-11-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984181203U JPS6196558U (en) 1984-11-29 1984-11-29

Publications (1)

Publication Number Publication Date
JPS6196558U true JPS6196558U (en) 1986-06-21

Family

ID=30738758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984181203U Pending JPS6196558U (en) 1984-11-29 1984-11-29

Country Status (1)

Country Link
JP (1) JPS6196558U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888316A (en) * 1994-09-16 1996-04-02 Nec Corp Hybrid ic and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888316A (en) * 1994-09-16 1996-04-02 Nec Corp Hybrid ic and its manufacture

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