JPS61100167U - - Google Patents

Info

Publication number
JPS61100167U
JPS61100167U JP18571084U JP18571084U JPS61100167U JP S61100167 U JPS61100167 U JP S61100167U JP 18571084 U JP18571084 U JP 18571084U JP 18571084 U JP18571084 U JP 18571084U JP S61100167 U JPS61100167 U JP S61100167U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
wiring board
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18571084U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18571084U priority Critical patent/JPS61100167U/ja
Publication of JPS61100167U publication Critical patent/JPS61100167U/ja
Pending legal-status Critical Current

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Landscapes

  • Structure Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例の混成集積回路
装置を示す斜視図、第2図は本考案の第2の実施
例の混成集積回路装置を示す平面図、第3図は第
2図のA―A′線に沿つて切断しその断面を見た
断面図である。 尚図において、1,1′,4……セラミツク配
線基板、2,2′……厚膜配線パターン、3′3
″,3……溝部、5……搭載部品、6……外装
樹脂。
FIG. 1 is a perspective view showing a hybrid integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a plan view showing a hybrid integrated circuit device according to a second embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view taken along the line AA' in the figure. In the figure, 1, 1', 4...ceramic wiring board, 2, 2'...thick film wiring pattern, 3'3
″, 3...Groove portion, 5...Mounted parts, 6...Exterior resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子や受動素子、配線等が設けられるセ
ラミツク配線基板に、溝を設けたことを特徴とす
る混成集積回路装置。
A hybrid integrated circuit device characterized in that a groove is provided in a ceramic wiring board on which semiconductor elements, passive elements, wiring, etc. are provided.
JP18571084U 1984-12-07 1984-12-07 Pending JPS61100167U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18571084U JPS61100167U (en) 1984-12-07 1984-12-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18571084U JPS61100167U (en) 1984-12-07 1984-12-07

Publications (1)

Publication Number Publication Date
JPS61100167U true JPS61100167U (en) 1986-06-26

Family

ID=30743176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18571084U Pending JPS61100167U (en) 1984-12-07 1984-12-07

Country Status (1)

Country Link
JP (1) JPS61100167U (en)

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