JPS6418778U - - Google Patents

Info

Publication number
JPS6418778U
JPS6418778U JP1987113376U JP11337687U JPS6418778U JP S6418778 U JPS6418778 U JP S6418778U JP 1987113376 U JP1987113376 U JP 1987113376U JP 11337687 U JP11337687 U JP 11337687U JP S6418778 U JPS6418778 U JP S6418778U
Authority
JP
Japan
Prior art keywords
thick film
film substrate
integrated circuit
hybrid integrated
location
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987113376U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987113376U priority Critical patent/JPS6418778U/ja
Publication of JPS6418778U publication Critical patent/JPS6418778U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の厚膜基板の断面図、第２図は
従来の厚膜基板の断面図である。 １……混成集積回路用厚膜基板、２……ＩＣチ
ツプ、３……ミニモールドＴｒ、４……チツプコ
ンデンサ、５……外部リード。 FIG. 1 is a sectional view of a thick film substrate of the present invention, and FIG. 2 is a sectional view of a conventional thick film substrate. 1... Thick film substrate for hybrid integrated circuit, 2... IC chip, 3... Mini mold transistor, 4... Chip capacitor, 5... External lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 混成集積回路用厚膜基板において部品が搭載さ
れる個所の導電体膜が厚膜基板の所定領域に形成
された凹部の底面に設けられていることを特徴と
する混成集積回路用厚膜基板。 1. A thick film substrate for a hybrid integrated circuit, characterized in that a conductive film at a location where a component is mounted in the thick film substrate for a hybrid integrated circuit is provided on the bottom surface of a recess formed in a predetermined area of the thick film substrate.
JP1987113376U 1987-07-23 1987-07-23 Pending JPS6418778U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987113376U JPS6418778U (en) 1987-07-23 1987-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987113376U JPS6418778U (en) 1987-07-23 1987-07-23

Publications (1)

Publication Number Publication Date
JPS6418778U true JPS6418778U (en) 1989-01-30

Family

ID=31353157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987113376U Pending JPS6418778U (en) 1987-07-23 1987-07-23

Country Status (1)

Country Link
JP (1) JPS6418778U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191061A (en) * 1996-01-09 1997-07-22 Nec Corp Chip carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191061A (en) * 1996-01-09 1997-07-22 Nec Corp Chip carrier

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