JPH02142533U - - Google Patents

Info

Publication number
JPH02142533U
JPH02142533U JP5134389U JP5134389U JPH02142533U JP H02142533 U JPH02142533 U JP H02142533U JP 5134389 U JP5134389 U JP 5134389U JP 5134389 U JP5134389 U JP 5134389U JP H02142533 U JPH02142533 U JP H02142533U
Authority
JP
Japan
Prior art keywords
chip carrier
mounting surface
chip
semiconductor
metallization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5134389U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5134389U priority Critical patent/JPH02142533U/ja
Publication of JPH02142533U publication Critical patent/JPH02142533U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示しており、同図
ａは平面図、同図ｂはそのＡ−Ａ線に沿う断面図
、第２図は本考案の他の実施例の平面図、第３図
は従来のチツプキヤリアを示しており、同図ａは
平面図、同図ｂはそのＢ−Ｂ線に沿う断面図であ
る。 １……チツプキヤリアケース、２……マウント
面、３，３Ａ……溝、４……内部リード、５……
外部接続端子。 Fig. 1 shows an embodiment of the present invention; Fig. 1a is a plan view, Fig. 2b is a sectional view taken along line A-A, and Fig. 2 is a plan view of another embodiment of the invention. , FIG. 3 shows a conventional chip carrier, in which FIG. 3A is a plan view and FIG. 1...Chip carrier case, 2...Mount surface, 3, 3A...Groove, 4...Internal lead, 5...
External connection terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チツプキヤリアケースの内底面にメタライズで
形成したマウント面を有し、このマウント面に半
導体チツプをろ一材で接着してなるチツプキヤリ
アにおいて、前記マウント面には中央部から周辺
部にわたつてメタライズの厚さよりも浅い溝を形
成したことを特徴とする半導体集積回路装置のチ
ツプキヤリア。 A chip carrier has a mounting surface formed of metallization on the inner bottom surface of the chip carrier case, and a semiconductor chip is bonded to this mounting surface with a filter material. A chip carrier for a semiconductor integrated circuit device characterized by forming a groove shallower than its thickness.
JP5134389U 1989-04-28 1989-04-28 Pending JPH02142533U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5134389U JPH02142533U (en) 1989-04-28 1989-04-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5134389U JPH02142533U (en) 1989-04-28 1989-04-28

Publications (1)

Publication Number Publication Date
JPH02142533U true JPH02142533U (en) 1990-12-04

Family

ID=31570700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5134389U Pending JPH02142533U (en) 1989-04-28 1989-04-28

Country Status (1)

Country Link
JP (1) JPH02142533U (en)

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