JPH0348238U - - Google Patents
Info
- Publication number
- JPH0348238U JPH0348238U JP11023589U JP11023589U JPH0348238U JP H0348238 U JPH0348238 U JP H0348238U JP 11023589 U JP11023589 U JP 11023589U JP 11023589 U JP11023589 U JP 11023589U JP H0348238 U JPH0348238 U JP H0348238U
- Authority
- JP
- Japan
- Prior art keywords
- island
- lead
- integrated
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 8
- 238000002955 isolation Methods 0.000 claims 2
- 239000011347 resin Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 claims 2
- 238000007789 sealing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Description
第１図と第２図は夫々本考案を説明する為の平
面図と側面図、第３図と第４図は夫々従来例を説
明する為の平面図と断面図である。
1 and 2 are a plan view and a side view, respectively, for explaining the present invention, and FIGS. 3 and 4 are a plan view and a sectional view, respectively, for explaining a conventional example.
Claims (1)
のアイランドに一体化して延在する外部接続用の
一体化リードと、前記アイランドとは分離され前
記アイランドに近接するように延在する外部接続
用の分離リードと、前記半導体チツプを含む主要
部を封止した樹脂とを具備する表面実装型半導体
装置において、 前記アイランドを、前記樹脂内において隣接す
る分離リード側に拡大し、その分離リードとアイ
ランドとを一体化することにより前記アイランド
の面積を増大したことを特徴とする表面実装型半
導体装置。 (2) 前記半導体チツプは２端子素子であること
を特徴とする請求項第１項に記載の表面実装型半
導体装置。 (3) 前記アイランド上に、前記一体化リードか
ら前記一体化した分離リードにまで達する大きさ
の半導体チツプを固着したことを特徴とする請求
項第１項に記載の表面実装型半導体装置。[Claims for Utility Model Registration] (1) An island to which a semiconductor chip is fixed, an integrated lead for external connection that is integrated with this island and extends, and an integrated lead that is separated from the island and is close to the island. In a surface mount semiconductor device comprising an extending isolation lead for external connection and a resin sealing a main part including the semiconductor chip, the island is expanded to the adjacent isolation lead side within the resin. , a surface mount type semiconductor device characterized in that the area of the island is increased by integrating the separated lead and the island. (2) The surface-mounted semiconductor device according to claim 1, wherein the semiconductor chip is a two-terminal device. (3) The surface mount type semiconductor device according to claim 1, wherein a semiconductor chip having a size that reaches from the integrated lead to the integrated separated lead is fixed on the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11023589U JPH0348238U (en) | 1989-09-19 | 1989-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11023589U JPH0348238U (en) | 1989-09-19 | 1989-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0348238U true JPH0348238U (en) | 1991-05-08 |
Family
ID=31658783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11023589U Pending JPH0348238U (en) | 1989-09-19 | 1989-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0348238U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009537182A (en) * | 2006-05-18 | 2009-10-29 | バビリス ファコ ソシエテ アノニム | Improved hair straightening device |
-
1989
- 1989-09-19 JP JP11023589U patent/JPH0348238U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009537182A (en) * | 2006-05-18 | 2009-10-29 | バビリス ファコ ソシエテ アノニム | Improved hair straightening device |