JPS60121650U - Chippukiyariya - Google Patents
ChippukiyariyaInfo
- Publication number
- JPS60121650U JPS60121650U JP1984009813U JP981384U JPS60121650U JP S60121650 U JPS60121650 U JP S60121650U JP 1984009813 U JP1984009813 U JP 1984009813U JP 981384 U JP981384 U JP 981384U JP S60121650 U JPS60121650 U JP S60121650U
- Authority
- JP
- Japan
- Prior art keywords
- lid
- integrated circuit
- chippukiyariya
- semiconductor element
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のチップキャリアを示す断面図、第2図は
本考案の一実施例において、本体部と蓋部とを分解して
示す断面図、そして第3゛図は、第2図の本体部と蓋部
を組合せた本考案の一実施例を示す断面図である。
A・・・本体部、B・・・蓋体、1,1a・・・チップ
キャリア本体、1b・・・基体部、2・・・ワイヤ、3
,3a、3b・・・集積回路素子あるいは半導体素子、
4・・・内部電極、5・・・外部電極、6・・・封止剤
、7・・・蓋。FIG. 1 is a cross-sectional view showing a conventional chip carrier, FIG. 2 is an exploded cross-sectional view showing the main body and lid in an embodiment of the present invention, and FIG. 3 is a cross-sectional view of the conventional chip carrier. FIG. 3 is a sectional view showing an embodiment of the present invention in which the main body and the lid are combined. A... Main body part, B... Lid body, 1, 1a... Chip carrier main body, 1b... Base part, 2... Wire, 3
, 3a, 3b... integrated circuit element or semiconductor element,
4... Internal electrode, 5... External electrode, 6... Sealing agent, 7... Lid.
Claims (1)
相応位置に、集積回路素子あるいは半導体素子を実装し
た蓋体を配設したチップキャリア。A chip carrier in which a lid body with an integrated circuit element or semiconductor element mounted thereon is disposed at a position corresponding to the lid of a main body part on which the integrated circuit element or semiconductor element is mounted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984009813U JPS60121650U (en) | 1984-01-27 | 1984-01-27 | Chippukiyariya |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984009813U JPS60121650U (en) | 1984-01-27 | 1984-01-27 | Chippukiyariya |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60121650U true JPS60121650U (en) | 1985-08-16 |
Family
ID=30490387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984009813U Pending JPS60121650U (en) | 1984-01-27 | 1984-01-27 | Chippukiyariya |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60121650U (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62130533A (en) * | 1985-11-22 | 1987-06-12 | テキサス インスツルメンツ インコ−ポレイテツド | Chip carrier and circuit using it and manufacture of chip carrier |
JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
JP2015012077A (en) * | 2013-06-27 | 2015-01-19 | 京セラ株式会社 | Electronic component housing package, and electronic device |
-
1984
- 1984-01-27 JP JP1984009813U patent/JPS60121650U/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62130533A (en) * | 1985-11-22 | 1987-06-12 | テキサス インスツルメンツ インコ−ポレイテツド | Chip carrier and circuit using it and manufacture of chip carrier |
JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
JP2015012077A (en) * | 2013-06-27 | 2015-01-19 | 京セラ株式会社 | Electronic component housing package, and electronic device |
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