JPS5896276U - Measuring jig for integrated circuits - Google Patents

Measuring jig for integrated circuits

Info

Publication number
JPS5896276U
JPS5896276U JP19107681U JP19107681U JPS5896276U JP S5896276 U JPS5896276 U JP S5896276U JP 19107681 U JP19107681 U JP 19107681U JP 19107681 U JP19107681 U JP 19107681U JP S5896276 U JPS5896276 U JP S5896276U
Authority
JP
Japan
Prior art keywords
integrated circuits
measuring jig
recess
external lead
contact pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19107681U
Other languages
Japanese (ja)
Inventor
広瀬　茂春
寛 石野
Original Assignee
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 沖電気工業株式会社 filed Critical 沖電気工業株式会社
Priority to JP19107681U priority Critical patent/JPS5896276U/en
Publication of JPS5896276U publication Critical patent/JPS5896276U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示す断面図、第２図は他の従来例を示
す断面図、第３図は本考案の一実施例を示す断面図であ
る。 ５・・・デュアルインライン型半導体集積回路装置、６
・・・外部リード、１３・・・治具本体、１４・・・凹
部、１５・・・接触ピン、１６・・・傾斜面、１７・・
・端子。FIG. 1 is a sectional view showing a conventional example, FIG. 2 is a sectional view showing another conventional example, and FIG. 3 is a sectional view showing an embodiment of the present invention. 5...Dual in-line semiconductor integrated circuit device, 6
... External lead, 13 ... Jig body, 14 ... Recess, 15 ... Contact pin, 16 ... Inclined surface, 17 ...
・Terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 治具本体に凹部を設け、該凹部内にデュアルインライン
型半導体集草回路装置の外部リードと対応する接触ピン
を配置すると共に、該接触ピンの上面を前記外部リード
がスライドして接触するための傾斜面としたことを特徴
とする集積回路用測定治具。A recess is provided in the jig main body, and a contact pin corresponding to the external lead of the dual in-line semiconductor grass collector circuit device is arranged in the recess, and the external lead slides on the upper surface of the contact pin to make contact. A measuring jig for integrated circuits characterized by having an inclined surface.
JP19107681U 1981-12-23 1981-12-23 Measuring jig for integrated circuits Pending JPS5896276U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19107681U JPS5896276U (en) 1981-12-23 1981-12-23 Measuring jig for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19107681U JPS5896276U (en) 1981-12-23 1981-12-23 Measuring jig for integrated circuits

Publications (1)

Publication Number Publication Date
JPS5896276U true JPS5896276U (en) 1983-06-30

Family

ID=30104559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19107681U Pending JPS5896276U (en) 1981-12-23 1981-12-23 Measuring jig for integrated circuits

Country Status (1)

Country Link
JP (1) JPS5896276U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005516A (en) * 1997-06-30 1999-01-25 윤종용 Test Sockets for Semiconductor Chip Package Testing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990005516A (en) * 1997-06-30 1999-01-25 윤종용 Test Sockets for Semiconductor Chip Package Testing

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