JPS60169860U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS60169860U
JPS60169860U JP5693284U JP5693284U JPS60169860U JP S60169860 U JPS60169860 U JP S60169860U JP 5693284 U JP5693284 U JP 5693284U JP 5693284 U JP5693284 U JP 5693284U JP S60169860 U JPS60169860 U JP S60169860U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrate
recorded
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5693284U
Other languages
Japanese (ja)
Inventor
二宮　秀樹
Original Assignee
株式会社　富士電機総合研究所
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社　富士電機総合研究所, 富士電機株式会社 filed Critical 株式会社　富士電機総合研究所
Priority to JP5693284U priority Critical patent/JPS60169860U/en
Publication of JPS60169860U publication Critical patent/JPS60169860U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の混成集積回路の部分的断面図、第２図
ａは第１図とは異る実施例と示した正面図、第２図すは
同じく断面図、第３図は従来の混成集積回路の部分的断
面図である。 １・・・基板、２．３．７・・・ＩＣチップ、４・・・
突起電極、５・・・フリップチップ、８・・・スペーサ
。Figure 1 is a partial sectional view of the hybrid integrated circuit of the present invention, Figure 2a is a front view showing a different embodiment from Figure 1, Figure 2 is also a sectional view, and Figure 3 is a conventional 1 is a partial cross-sectional view of a hybrid integrated circuit of FIG. 1... Board, 2.3.7... IC chip, 4...
Projection electrode, 5... flip chip, 8... spacer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板上に該基板に垂直な方向に複数個のＩＣチップ
が重なって配置されたことを特徴とする混成集積回路。A hybrid integrated circuit characterized in that a plurality of IC chips are arranged on an insulating substrate in a direction perpendicular to the substrate, overlapping each other.
JP5693284U 1984-04-18 1984-04-18 hybrid integrated circuit Pending JPS60169860U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5693284U JPS60169860U (en) 1984-04-18 1984-04-18 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5693284U JPS60169860U (en) 1984-04-18 1984-04-18 hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60169860U true JPS60169860U (en) 1985-11-11

Family

ID=30580999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5693284U Pending JPS60169860U (en) 1984-04-18 1984-04-18 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60169860U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172172U (en) * 1987-04-30 1988-11-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172172U (en) * 1987-04-30 1988-11-09

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