JPS58109254U - Chip carrier for face-down connected chips - Google Patents

Chip carrier for face-down connected chips

Info

Publication number
JPS58109254U
JPS58109254U JP506982U JP506982U JPS58109254U JP S58109254 U JPS58109254 U JP S58109254U JP 506982 U JP506982 U JP 506982U JP 506982 U JP506982 U JP 506982U JP S58109254 U JPS58109254 U JP S58109254U
Authority
JP
Japan
Prior art keywords
chip
face
chip carrier
dimension
down connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP506982U
Other languages
Japanese (ja)
Inventor
草野 正昭
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP506982U priority Critical patent/JPS58109254U/en
Publication of JPS58109254U publication Critical patent/JPS58109254U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来公知のチップキャリヤーの断面図第2図は
本考案でなるチップキャリヤーの一実施例を示す断面図
、第3図はその平面図、第4図は本考案のキャビティ寸
法を示す断面図、第5図は、導体パターンにはんだ層を
形成した断面図である。 11・・・・・・第1のセラミック層、12・・・・・
・第2のセラミック層、13・・・・・・セラミックキ
ャップ、15・・・・・・フェースダウン接続形集積回
路チップ、16・・・・・・第1の導体パターン、16
A・・・・・・チップ接続ペターン、17・・・・・・
第2の導体パターン、1−8′・・・・・・封止用導体
パターン、19・・・・・・外部接続用導体パターン、
20・・・・・・はんだ接続部、21・・・   。 ・・・はんだ封止層、22・・・・・・はんだ層、W・
・・・・・チップ電t1寸L s・・・・・・スペース
、C・・・・・・キャビティ寸法。
Fig. 1 is a sectional view of a conventionally known chip carrier; Fig. 2 is a sectional view showing an embodiment of the chip carrier of the present invention; Fig. 3 is a plan view thereof; and Fig. 4 shows the cavity dimensions of the present invention. The cross-sectional view, FIG. 5, is a cross-sectional view in which a solder layer is formed on a conductor pattern. 11...First ceramic layer, 12...
- Second ceramic layer, 13...Ceramic cap, 15...Face-down connection type integrated circuit chip, 16...First conductor pattern, 16
A...Chip connection pattern, 17...
2nd conductor pattern, 1-8'...conductor pattern for sealing, 19...conductor pattern for external connection,
20...Solder connection part, 21... ...Solder sealing layer, 22...Solder layer, W.
...Chip electric t1 dimension L s ... Space, C ... Cavity dimension.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フェースダウン形集積回路チップのはんだ電極と接続す
る第1の導体パターンを形成した第1のセラミック層と
、該第1のセラミック層上に封止用の第2の導体パター
ンを形成したチップ収納キャビティを有する第2のセラ
ミック層より成り、該キャビティ寸法とチップ外形寸法
とのスペースを、チップ電極寸法に等しいか、それ以下
としたことを特徴とするフェースダウン接続形チップ用
チップキャリヤー。  ゛
A first ceramic layer having a first conductive pattern connected to a solder electrode of a face-down integrated circuit chip, and a chip housing cavity having a second conductive pattern for sealing formed on the first ceramic layer. 1. A chip carrier for a face-down connected chip, characterized in that the space between the cavity dimension and the chip outer dimension is equal to or less than the chip electrode dimension.゛
JP506982U 1982-01-20 1982-01-20 Chip carrier for face-down connected chips Pending JPS58109254U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP506982U JPS58109254U (en) 1982-01-20 1982-01-20 Chip carrier for face-down connected chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP506982U JPS58109254U (en) 1982-01-20 1982-01-20 Chip carrier for face-down connected chips

Publications (1)

Publication Number Publication Date
JPS58109254U true JPS58109254U (en) 1983-07-25

Family

ID=30017883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP506982U Pending JPS58109254U (en) 1982-01-20 1982-01-20 Chip carrier for face-down connected chips

Country Status (1)

Country Link
JP (1) JPS58109254U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254655A (en) * 1994-11-21 1995-10-03 Matsushita Electron Corp Electronic device and manufacture thereof
JPH08264676A (en) * 1996-04-24 1996-10-11 Matsushita Electron Corp Electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254655A (en) * 1994-11-21 1995-10-03 Matsushita Electron Corp Electronic device and manufacture thereof
JPH08264676A (en) * 1996-04-24 1996-10-11 Matsushita Electron Corp Electronic component

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