JPH03122548U - - Google Patents
Info
- Publication number
- JPH03122548U JPH03122548U JP1990031397U JP3139790U JPH03122548U JP H03122548 U JPH03122548 U JP H03122548U JP 1990031397 U JP1990031397 U JP 1990031397U JP 3139790 U JP3139790 U JP 3139790U JP H03122548 U JPH03122548 U JP H03122548U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- bonded
- metal fin
- semiconductor device
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Description
第1図はこの考案の一実施例による半導体装置
の断面図、第2図は第1図の斜視図、第3図aは
従来の半導体装置の断面図、第3図bはa図を誇
張して示した説明断面図、第4図は第3図aの斜
視図である。
図において、1はセラミツク基板、2は金属フ
イン、3はセラミツク基板1と金属フイン2を接
着する半田を示す。なお、図中、同一符号は同一
、または相当部分を示す。
Figure 1 is a sectional view of a semiconductor device according to an embodiment of the invention, Figure 2 is a perspective view of Figure 1, Figure 3a is a sectional view of a conventional semiconductor device, and Figure 3b is an exaggerated version of Figure a. FIG. 4 is a perspective view of FIG. 3a. In the figure, 1 is a ceramic substrate, 2 is a metal fin, and 3 is solder for bonding the ceramic substrate 1 and the metal fin 2 together. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ツク基板に接着される金属フインを備え、前記接
着される金属フインが多数に分割されていること
を特徴とする半導体装置。 1. A semiconductor device comprising a ceramic substrate on which a circuit is formed and a metal fin bonded to the ceramic substrate, wherein the metal fin to be bonded is divided into many pieces.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990031397U JPH03122548U (en) | 1990-03-27 | 1990-03-27 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990031397U JPH03122548U (en) | 1990-03-27 | 1990-03-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03122548U true JPH03122548U (en) | 1991-12-13 |
Family
ID=31534151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990031397U Pending JPH03122548U (en) | 1990-03-27 | 1990-03-27 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03122548U (en) |
-
1990
- 1990-03-27 JP JP1990031397U patent/JPH03122548U/ja active Pending
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