JPH01176950U - - Google Patents
Info
- Publication number
- JPH01176950U JPH01176950U JP1988073502U JP7350288U JPH01176950U JP H01176950 U JPH01176950 U JP H01176950U JP 1988073502 U JP1988073502 U JP 1988073502U JP 7350288 U JP7350288 U JP 7350288U JP H01176950 U JPH01176950 U JP H01176950U
- Authority
- JP
- Japan
- Prior art keywords
- package
- positioning groove
- semiconductor
- stacked
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図は考案の一実施例による上段ＩＣパツケ
ージの裏面の斜視図、第２図はこの考案の上段Ｉ
Ｃパツケージと下段ＩＣパツケージを組込んだ状
態の側面図、第３図は第２図のＩＣパツケージを
基板に挿入しはんだ付けをした状態の側面図、第
４図は従来のＩＣパツケージの裏面の斜視図、第
５図は従来のＩＣパツケージの部分断面斜視図で
ある。
図において、１は上段ＩＣパツケージ、２はリ
ード線、３は位置決め溝、４は下段ＩＣパツケー
ジ、５は基板、６ははんだを示す。なお、図中、
同一符号は同一、または相当部分を示す。
FIG. 1 is a perspective view of the back side of an upper IC package according to an embodiment of the invention, and FIG. 2 is an upper IC package according to an embodiment of the invention.
Figure 3 is a side view of the IC package shown in Figure 2 inserted into the board and soldered. Figure 4 is a side view of the back side of the conventional IC package. FIG. 5 is a partially sectional perspective view of a conventional IC package. In the figure, 1 is an upper IC package, 2 is a lead wire, 3 is a positioning groove, 4 is a lower IC package, 5 is a board, and 6 is solder. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.
Claims (1)
ージ構造において、上段のパツケージの裏面に凹
の部分を設け、下段のパツケージの位置決め溝に
利用したことを特徴とする半導体装置のパツケー
ジ構造。 A semiconductor package structure in which two semiconductor devices are stacked on a substrate, characterized in that a concave portion is provided on the back surface of the upper package and used as a positioning groove for the lower package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988073502U JPH01176950U (en) | 1988-06-01 | 1988-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988073502U JPH01176950U (en) | 1988-06-01 | 1988-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01176950U true JPH01176950U (en) | 1989-12-18 |
Family
ID=31298644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988073502U Pending JPH01176950U (en) | 1988-06-01 | 1988-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01176950U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| KR20030057186A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |
-
1988
- 1988-06-01 JP JP1988073502U patent/JPH01176950U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| KR20030057186A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |