JPH0363949U - - Google Patents
Info
- Publication number
- JPH0363949U JPH0363949U JP1989124715U JP12471589U JPH0363949U JP H0363949 U JPH0363949 U JP H0363949U JP 1989124715 U JP1989124715 U JP 1989124715U JP 12471589 U JP12471589 U JP 12471589U JP H0363949 U JPH0363949 U JP H0363949U
- Authority
- JP
- Japan
- Prior art keywords
- package cage
- package
- utility
- top surface
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Multi-Conductor Connections (AREA)
Description
第１図はこの考案の一実施例によるＩＣソケツ
トを示す断面図、第２図は従来のＩＣソケツトを
示す断面図である。
１……ＩＣパツケージ、２……リード、３……
ＩＣチツプ、４……ケーブル口、５……ケーブル
接点。なお、図中同一符号は同一、または相当部
分を示す。
FIG. 1 is a sectional view showing an IC socket according to an embodiment of this invention, and FIG. 2 is a sectional view showing a conventional IC socket. 1...IC package cage, 2...lead, 3...
IC chip, 4...cable port, 5...cable contact. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
えたことを特徴とするＩＣパツケージ。 An IC package cage characterized by having a cable socket on the top surface of the IC package cage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989124715U JPH0363949U (en) | 1989-10-25 | 1989-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989124715U JPH0363949U (en) | 1989-10-25 | 1989-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0363949U true JPH0363949U (en) | 1991-06-21 |
Family
ID=31672620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989124715U Pending JPH0363949U (en) | 1989-10-25 | 1989-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0363949U (en) |
-
1989
- 1989-10-25 JP JP1989124715U patent/JPH0363949U/ja active Pending