JPS64331U - - Google Patents
Info
- Publication number
- JPS64331U JPS64331U JP9412387U JP9412387U JPS64331U JP S64331 U JPS64331 U JP S64331U JP 9412387 U JP9412387 U JP 9412387U JP 9412387 U JP9412387 U JP 9412387U JP S64331 U JPS64331 U JP S64331U
- Authority
- JP
- Japan
- Prior art keywords
- elements
- utility
- scope
- registration request
- triangular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案一実施例図、第２図は従来の四
角チツプと本考案による三角形チツプの同一面積
での例である。
FIG. 1 is an example of an embodiment of the present invention, and FIG. 2 is an example of a conventional square chip and a triangular chip according to the present invention having the same area.
Claims (1)
半導体装置。 A semiconductor device in which elements are formed on a triangular semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9412387U JPS64331U (en) | 1987-06-19 | 1987-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9412387U JPS64331U (en) | 1987-06-19 | 1987-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS64331U true JPS64331U (en) | 1989-01-05 |
Family
ID=30957279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9412387U Pending JPS64331U (en) | 1987-06-19 | 1987-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS64331U (en) |
-
1987
- 1987-06-19 JP JP9412387U patent/JPS64331U/ja active Pending