JPH02742U - - Google Patents
Info
- Publication number
- JPH02742U JPH02742U JP7742888U JP7742888U JPH02742U JP H02742 U JPH02742 U JP H02742U JP 7742888 U JP7742888 U JP 7742888U JP 7742888 U JP7742888 U JP 7742888U JP H02742 U JPH02742 U JP H02742U
- Authority
- JP
- Japan
- Prior art keywords
- package
- main surfaces
- semiconductor device
- lead
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂおよびｃはそれぞれ本考案の一実
施例を示す半導体装置の平面図、Ａ−Ａ′断面図
および側面図、第２図ａおよびｂはそれぞれ従来
半導体装置の平面図および側面図である。
１……リード、２……パツケージ。
Figures 1a, b and c are a plan view, A-A' sectional view and side view of a semiconductor device showing an embodiment of the present invention, respectively, and Figures 2a and b are a plan view and side view of a conventional semiconductor device, respectively. It is a diagram. 1...Lead, 2...Package.
Claims (1)
れ、且つ、前記各リードはパツケージの前記２主
面とそれぞれ同一平面に一体化され露出されてい
ることを特徴とする半導体装置。 A semiconductor device characterized in that a plurality of leads are led out on two main surfaces of a package, and each lead is integrated and exposed on the same plane as the two main surfaces of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7742888U JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7742888U JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02742U true JPH02742U (en) | 1990-01-05 |
Family
ID=31302413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7742888U Pending JPH02742U (en) | 1988-06-10 | 1988-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02742U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006287131A (en) * | 2005-04-04 | 2006-10-19 | Sony Corp | Semiconductor package and its manufacturing method |
-
1988
- 1988-06-10 JP JP7742888U patent/JPH02742U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006287131A (en) * | 2005-04-04 | 2006-10-19 | Sony Corp | Semiconductor package and its manufacturing method |
| JP4600124B2 (en) * | 2005-04-04 | 2010-12-15 | ソニー株式会社 | Manufacturing method of semiconductor package |