JPH02102729U - - Google Patents
Info
- Publication number
- JPH02102729U JPH02102729U JP1132389U JP1132389U JPH02102729U JP H02102729 U JPH02102729 U JP H02102729U JP 1132389 U JP1132389 U JP 1132389U JP 1132389 U JP1132389 U JP 1132389U JP H02102729 U JPH02102729 U JP H02102729U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- utility
- semiconductor chip
- die part
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図ａは、本考案の一実施例を示す平面図。
第１図ｂは、第１図ａのＡ部断面図。第２図ａは
、従来のＩＣダイパツト構造を示す平面図。第２
図ｂは、第２図ａのＡ部断面図。第３図、第４図
は、本考案の実施例を示す平面図。
１……回路基板、２……ＩＣチツプ、３……Ｉ
Ｃダイパツト、４……接着剤、５……へこみ。
FIG. 1a is a plan view showing an embodiment of the present invention.
FIG. 1b is a sectional view of section A in FIG. 1a. FIG. 2a is a plan view showing a conventional IC die pad structure. Second
Figure b is a sectional view of section A in Figure 2a. 3 and 4 are plan views showing embodiments of the present invention. 1...Circuit board, 2...IC chip, 3...I
C die part, 4...adhesive, 5...dent.
Claims (1)
Ｃダイパツトが凹構造を有することを特徴とする
回路基板。 In a circuit board on which a semiconductor chip is mounted, I
A circuit board characterized in that a C die part has a concave structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1132389U JPH02102729U (en) | 1989-02-01 | 1989-02-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1132389U JPH02102729U (en) | 1989-02-01 | 1989-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102729U true JPH02102729U (en) | 1990-08-15 |
Family
ID=31219778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1132389U Pending JPH02102729U (en) | 1989-02-01 | 1989-02-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102729U (en) |
-
1989
- 1989-02-01 JP JP1132389U patent/JPH02102729U/ja active Pending