JPS6265847U - - Google Patents

Info

Publication number
JPS6265847U
JPS6265847U JP15818385U JP15818385U JPS6265847U JP S6265847 U JPS6265847 U JP S6265847U JP 15818385 U JP15818385 U JP 15818385U JP 15818385 U JP15818385 U JP 15818385U JP S6265847 U JPS6265847 U JP S6265847U
Authority
JP
Japan
Prior art keywords
facing
lead
package
flat package
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15818385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15818385U priority Critical patent/JPS6265847U/ja
Publication of JPS6265847U publication Critical patent/JPS6265847U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のフラツトパツケージの一実施
例を示す正面図、第2図は別の実施例を示す斜視
図、第3図は従来のフラツトパツケージおよびそ
の実装方法を示す断面図である。 1,5…パツケージ本体、2,6…リード、3
…回路基板、4…はんだ。
Fig. 1 is a front view showing one embodiment of the flat package of the present invention, Fig. 2 is a perspective view showing another embodiment, and Fig. 3 is a sectional view showing a conventional flat package and its mounting method. be. 1, 5...Package body, 2,6...Lead, 3
...Circuit board, 4...Solder.

Claims (1)

【実用新案登録請求の範囲】 (1) 複数のICチツプをパツケージ内に封入し
てなるパツケージ本体と、前記ICチツプに電気
的に接続され前記基体の側面から突設された複数
本のリードとからなるフラツトパツケージにおい
て、前記リードが接続端面を前記本体の一方の側
面側に向け、かつこの側面より突出させて形成さ
れたものと、接続端面を他方の側面側に向け、か
つこの側面より突出させて形成されたものとから
構成されていることを特徴とするフラツトパツケ
ージ。 (2) 接続端面を一方の側面側に向けて形成され
たリードと他方の側面側に向けて形成されたリー
ドとが、これらの基部において直接電気的に接続
されていることを特徴とする実用新案登録請求の
範囲第1項記載のフラツトパツケージ。
[Claims for Utility Model Registration] (1) A package body comprising a plurality of IC chips enclosed in a package, and a plurality of leads electrically connected to the IC chips and protruding from the side surface of the base body. In the flat package, the lead has a connection end face facing one side of the main body and protrudes from this side, and a flat package with the lead facing the other side and protruding from this side. A flat package characterized by comprising a protruding part and a protruding part. (2) A practical device characterized in that a lead formed with the connecting end face facing one side face and a lead formed facing the other side face are directly electrically connected at their bases. A flat package according to claim 1 of patent registration.
JP15818385U 1985-10-15 1985-10-15 Pending JPS6265847U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15818385U JPS6265847U (en) 1985-10-15 1985-10-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15818385U JPS6265847U (en) 1985-10-15 1985-10-15

Publications (1)

Publication Number Publication Date
JPS6265847U true JPS6265847U (en) 1987-04-23

Family

ID=31081433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15818385U Pending JPS6265847U (en) 1985-10-15 1985-10-15

Country Status (1)

Country Link
JP (1) JPS6265847U (en)

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