JPS62201941U - - Google Patents
Info
- Publication number
- JPS62201941U JPS62201941U JP1986090677U JP9067786U JPS62201941U JP S62201941 U JPS62201941 U JP S62201941U JP 1986090677 U JP1986090677 U JP 1986090677U JP 9067786 U JP9067786 U JP 9067786U JP S62201941 U JPS62201941 U JP S62201941U
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- external lead
- receiving notch
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図は本考案によるパツケージの一実施例を
示す斜視図、第2図は第1図におけるリード受け
用切込み部と外部リード端子の関係を示す一部断
面図、第3図は上記実施例のパツケージを実装し
た時の状態を示す一部断面図、第4図は本考案に
よる他の実施例を示す斜視図、第5図aおよびb
は本考案による別の実施例をそれぞれ示す一部断
面図、第6図は従来のパツケージの一例を示す斜
視図、第7図は第6図におけるリード受け部と外
部リード端子の関係を示す一部断面図、第8図は
第6図のパツケージを実装したときの状態を示す
一部断面図である。
1…パツケージ本体、2…J形のリード(外部
リード端子)、3…実装基板、4…半田、11…
パツケージ本体の側面、12…パツケージ本体の
下面、13,14,15,16…リード受け用切
込み部、21…外部リード端子の先端部、31…
マウントパツド。
Fig. 1 is a perspective view showing an embodiment of the package according to the present invention, Fig. 2 is a partial sectional view showing the relationship between the lead receiving notch and the external lead terminal in Fig. 1, and Fig. 3 is the above-mentioned embodiment. FIG. 4 is a perspective view showing another embodiment of the present invention; FIGS. 5 a and b
6 is a partial sectional view showing another embodiment of the present invention, FIG. 6 is a perspective view showing an example of a conventional package, and FIG. 7 is a diagram showing the relationship between the lead receiving part and the external lead terminal in FIG. 6. FIG. 8 is a partial sectional view showing the state when the package of FIG. 6 is mounted. 1...Package body, 2...J-shaped lead (external lead terminal), 3...mounting board, 4...solder, 11...
Side surface of package body, 12... Bottom surface of package body, 13, 14, 15, 16... Lead receiving notch, 21... Tip of external lead terminal, 31...
Mount Pad.
Claims (1)
本体の少なくとも1つの側面に沿つて下方に延び
る複数のJ形の外部リード端子を有する集積回路
用パツケージにおいて、前記パツケージ本体の側
面と下面の境界部に、前記各外部リード端子の先
端部を保持するためのリード受け用切込み部を設
けたことを特徴とする集積回路用パツケージ。 (2) リード受け用切込み部を外部リード端子毎
に分割して設けたことを特徴とする実用新案登録
請求の範囲第1項記載の集積回路用パツケージ。[Claims for Utility Model Registration] (1) In an integrated circuit package having a plurality of J-shaped external lead terminals extending downward along at least one side of a package body in which an integrated circuit chip is sealed with resin, 1. A package for an integrated circuit, characterized in that a lead-receiving notch for holding the tip of each of the external lead terminals is provided at the boundary between the side surface and the bottom surface of the main body. (2) The package for an integrated circuit according to claim 1, wherein the lead receiving notch is divided for each external lead terminal.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986090677U JPS62201941U (en) | 1986-06-13 | 1986-06-13 | |
KR2019860022015U KR900003885Y1 (en) | 1986-06-13 | 1986-12-30 | Package for integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986090677U JPS62201941U (en) | 1986-06-13 | 1986-06-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62201941U true JPS62201941U (en) | 1987-12-23 |
Family
ID=30950761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986090677U Pending JPS62201941U (en) | 1986-06-13 | 1986-06-13 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS62201941U (en) |
KR (1) | KR900003885Y1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100422439B1 (en) * | 1997-01-15 | 2004-05-17 | 페어차일드코리아반도체 주식회사 | Pd limiting circuit for motor driver ic |
-
1986
- 1986-06-13 JP JP1986090677U patent/JPS62201941U/ja active Pending
- 1986-12-30 KR KR2019860022015U patent/KR900003885Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR880001342U (en) | 1988-03-15 |
KR900003885Y1 (en) | 1990-05-03 |
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