JPS59104539U - Chippukiyariya - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the most typical conventional chip carrier structure, and FIGS. 2 and 3 are a cross-sectional view and a rear view showing an embodiment of the new chip carrier structure based on the present invention. - In the figure, 1.1 is a chip board, 2 is a cavity, 3 is a semiconductor integrated circuit chip, 4 is a connection pad, 5 is an external connection terminal, 6 is a connection part, 7 is a central connection pad, 8 is a through hole, 9 is a The center connection portion and 10 indicate the center external connection terminal, respectively.

Claims (1)

[Scope of utility model registration request] A chip cavity that accommodates and mounts a semiconductor integrated circuit chip, a chip substrate, and a plurality of connecting parts formed on the chip substrate and extending from the bottom surface of the chip cavity through the front surface and side surfaces of the chip substrate to the connecting portion provided on the back surface. In a chip carrier composed of external connection terminals,
Furthermore, one or more central external connection terminals are connected from the bottom surface of the chip cavity to a central connection section larger than the connection section of the external connection terminals provided at the center of the back surface of the chip substrate through a through hole or a peer hole. A chip carrier characterized by having.