JPS6133451U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS6133451U
JPS6133451U JP11731784U JP11731784U JPS6133451U JP S6133451 U JPS6133451 U JP S6133451U JP 11731784 U JP11731784 U JP 11731784U JP 11731784 U JP11731784 U JP 11731784U JP S6133451 U JPS6133451 U JP S6133451U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
double
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11731784U
Other languages
Japanese (ja)
Inventor
豊 斉藤
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP11731784U priority Critical patent/JPS6133451U/en
Publication of JPS6133451U publication Critical patent/JPS6133451U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａは本考案による混成集積回路装置を示す表平面
図、ｂは裏面図、第２図ａは両面ショート端子を示す斜
視図、ｂは分解斜視図、第３図ａは両面パターンをもつ
従来における混成集積回路装置を示す平面図、ｂは裏面
図である。 １・・・回路基板、２・・・搭載部品、３・・・スルー
ホール、４・・・両面ショート端子、５・・・絶縁体、
６・・・リード。Fig. 1a is a top plan view showing a hybrid integrated circuit device according to the present invention, b is a back view, Fig. 2a is a perspective view showing a double-sided short terminal, b is an exploded perspective view, and Fig. 3a is a double-sided pattern. 1 is a plan view showing a conventional hybrid integrated circuit device, and b is a back view. 1... Circuit board, 2... Mounted component, 3... Through hole, 4... Double-sided short terminal, 5... Insulator,
6...Lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 両面に回路パターンをもつ混成集積回路装置の回路基板
の周縁に表パターンと裏パターンを電気゜ 的に接続す
る“両面ショート端子を取付けたことを特徴とする混成
集積回路装置。A hybrid integrated circuit device having circuit patterns on both sides, characterized in that a double-sided shorting terminal is attached to the periphery of the circuit board to electrically connect the front pattern and the back pattern.
JP11731784U 1984-07-31 1984-07-31 Hybrid integrated circuit device Pending JPS6133451U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11731784U JPS6133451U (en) 1984-07-31 1984-07-31 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11731784U JPS6133451U (en) 1984-07-31 1984-07-31 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6133451U true JPS6133451U (en) 1986-02-28

Family

ID=30676230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11731784U Pending JPS6133451U (en) 1984-07-31 1984-07-31 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6133451U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08233298A (en) * 1996-03-07 1996-09-10 Sharp Corp Electric carpet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08233298A (en) * 1996-03-07 1996-09-10 Sharp Corp Electric carpet

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