JPS60181073U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS60181073U
JPS60181073U JP7023284U JP7023284U JPS60181073U JP S60181073 U JPS60181073 U JP S60181073U JP 7023284 U JP7023284 U JP 7023284U JP 7023284 U JP7023284 U JP 7023284U JP S60181073 U JPS60181073 U JP S60181073U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
electrical components
membrane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7023284U
Other languages
Japanese (ja)
Inventor
長岡　亮一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7023284U priority Critical patent/JPS60181073U/en
Publication of JPS60181073U publication Critical patent/JPS60181073U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る混成集積回路装置の一実施例を示
す斜視図、第２図は従来の混成集積回路装置の斜視図で
ある。 図において、６・・・角形ブロック、７・・・ｖ字溝、
８・・・自立性をもたない電気部品、９・・・リード、
１０・・・絶縁基板、１１・・・膜回路。FIG. 1 is a perspective view showing an embodiment of a hybrid integrated circuit device according to the present invention, and FIG. 2 is a perspective view of a conventional hybrid integrated circuit device. In the figure, 6... square block, 7... V-shaped groove,
8... Electrical parts that do not have independence, 9... Leads,
10... Insulating substrate, 11... Membrane circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板上に膜回路を形成した回路基板に電気部品を搭
載してなる混成集積回路装置において、自立性をもたな
い電気部品の端子を回路基板上に設けた導電性ブロック
上に支持させるとともに、該ブロックを介して電子部品
を膜回路に電気的に接続したことを特徴とする混成集積
回路装置。In a hybrid integrated circuit device in which electrical components are mounted on a circuit board with a membrane circuit formed on an insulating substrate, the terminals of the electrical components that do not have independence are supported on conductive blocks provided on the circuit board, and , a hybrid integrated circuit device characterized in that an electronic component is electrically connected to a membrane circuit through the block.
JP7023284U 1984-05-14 1984-05-14 Hybrid integrated circuit device Pending JPS60181073U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7023284U JPS60181073U (en) 1984-05-14 1984-05-14 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7023284U JPS60181073U (en) 1984-05-14 1984-05-14 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60181073U true JPS60181073U (en) 1985-12-02

Family

ID=30606642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7023284U Pending JPS60181073U (en) 1984-05-14 1984-05-14 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60181073U (en)

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