JPS58175661U - Highly integrated hybrid integrated circuit - Google Patents
Highly integrated hybrid integrated circuitInfo
- Publication number
- JPS58175661U JPS58175661U JP7316882U JP7316882U JPS58175661U JP S58175661 U JPS58175661 U JP S58175661U JP 7316882 U JP7316882 U JP 7316882U JP 7316882 U JP7316882 U JP 7316882U JP S58175661 U JPS58175661 U JP S58175661U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- integrated circuit
- circuit
- highly
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案に係る高集積混成集積回路の実施例を示す
もので、第1図は高集積混成集積回路の正面断面図、第
2図は同一部破断外観斜視図である。The drawings show an embodiment of a highly integrated hybrid integrated circuit according to the present invention. FIG. 1 is a front sectional view of the highly integrated hybrid integrated circuit, and FIG. 2 is a partially cutaway external perspective view of the same.
Claims (1)
1のパターンと接続させて半導体素子を搭載し、前記セ
ラミック基板の上面に前記半導体素子を密閉するセラミ
ックケースを取り付けるとともに、前記セラミック基板
の側面に、該側面に−前記第1の回路と接続して形成さ
れた第2のパターンと接続させて密閉を必−としない回
路部品を搭載し、さらに前記セラミック基板の下部に、
前記第2のパターンと接続される実装用接続部を設けた
ことを特徴とする高集積混成集積回路。A semiconductor element is mounted on the upper surface of a rectangular ceramic substrate in connection with a first pattern formed on the upper surface, a ceramic case for sealing the semiconductor element is attached to the upper surface of the ceramic substrate, and a side surface of the ceramic substrate is mounted. A circuit component that does not require sealing is mounted on the side surface of the ceramic substrate by being connected to a second pattern formed in connection with the first circuit, and further, a circuit component that does not require sealing is mounted on the lower part of the ceramic substrate.
A highly integrated hybrid integrated circuit characterized in that a mounting connection part is provided to be connected to the second pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7316882U JPS58175661U (en) | 1982-05-19 | 1982-05-19 | Highly integrated hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7316882U JPS58175661U (en) | 1982-05-19 | 1982-05-19 | Highly integrated hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58175661U true JPS58175661U (en) | 1983-11-24 |
Family
ID=30082691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7316882U Pending JPS58175661U (en) | 1982-05-19 | 1982-05-19 | Highly integrated hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58175661U (en) |
-
1982
- 1982-05-19 JP JP7316882U patent/JPS58175661U/en active Pending
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