JPS58195445U - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPS58195445U
JPS58195445U JP1982093617U JP9361782U JPS58195445U JP S58195445 U JPS58195445 U JP S58195445U JP 1982093617 U JP1982093617 U JP 1982093617U JP 9361782 U JP9361782 U JP 9361782U JP S58195445 U JPS58195445 U JP S58195445U
Authority
JP
Japan
Prior art keywords
integrated circuit
package
semiconductor integrated
circuit package
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982093617U
Other languages
Japanese (ja)
Inventor
尾形　友博
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1982093617U priority Critical patent/JPS58195445U/en
Publication of JPS58195445U publication Critical patent/JPS58195445U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来例の半導体集積回路パッケージの斜視図
、第２図は、前回のＸ−Ｘ切断面図、第３図は、パッケ
ージ実装配線板の斜視図、第４図は、この考案の実施例
のを示すパッケージの縦断正面図である。 ９・・・・・・セラミックパッケージ、２ａ及び２ｂ・
・・・・・キャビティ、３ａ及び３ｂ・・・・・・集積
回路チップ、４ａ及び４ｂ・・・・・・ボンディングワ
イヤ、５ａ及び５ｂ・・・・・・パッド、６・・・・・
・リード端子。Fig. 1 is a perspective view of a conventional semiconductor integrated circuit package, Fig. 2 is a previous sectional view taken along line XX, Fig. 3 is a perspective view of a package mounting wiring board, and Fig. 4 is a perspective view of a conventional semiconductor integrated circuit package. FIG. 2 is a longitudinal sectional front view of a package showing an example of the present invention. 9... Ceramic package, 2a and 2b.
...Cavity, 3a and 3b...Integrated circuit chip, 4a and 4b...Bonding wire, 5a and 5b...Pad, 6...
・Lead terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミック等パッケージの両面に夫々キャビティを配設
し、各キャビティ内のパッケージに夫々集積回路チップ
を付設するとともに、両チップのためのリード端子配設
用のパッケージ面を共用するように該パッケージからリ
ード端子を導出させたことを特徴とする半導体集積回路
パッケージ。Cavities are provided on both sides of a ceramic package, and an integrated circuit chip is attached to each package in each cavity, and leads are placed from the package so that the package surface for providing lead terminals for both chips is shared. A semiconductor integrated circuit package characterized by having terminals led out.
JP1982093617U 1982-06-22 1982-06-22 Semiconductor integrated circuit package Pending JPS58195445U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982093617U JPS58195445U (en) 1982-06-22 1982-06-22 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982093617U JPS58195445U (en) 1982-06-22 1982-06-22 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPS58195445U true JPS58195445U (en) 1983-12-26

Family

ID=30224537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982093617U Pending JPS58195445U (en) 1982-06-22 1982-06-22 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPS58195445U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147850A (en) * 1987-12-04 1989-06-09 Fuji Electric Co Ltd Multilayer type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01147850A (en) * 1987-12-04 1989-06-09 Fuji Electric Co Ltd Multilayer type semiconductor device

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