JPS63164239U - - Google Patents

Info

Publication number
JPS63164239U
JPS63164239U JP1987057646U JP5764687U JPS63164239U JP S63164239 U JPS63164239 U JP S63164239U JP 1987057646 U JP1987057646 U JP 1987057646U JP 5764687 U JP5764687 U JP 5764687U JP S63164239 U JPS63164239 U JP S63164239U
Authority
JP
Japan
Prior art keywords
hole
frame
wiring board
thermally conductive
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987057646U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987057646U priority Critical patent/JPS63164239U/ja
Publication of JPS63164239U publication Critical patent/JPS63164239U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の断面図、第２図は
従来例の断面図である。 １……フレーム、１−１……第１のフレーム、
１−２……第２のフレーム、２……配線基板、３
……半導体チツプ、４……接着剤、５……ダイボ
ンデイング材、６……配線導体、７……引出線。 FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 1...frame, 1-1...first frame,
1-2...Second frame, 2...Wiring board, 3
... semiconductor chip, 4 ... adhesive, 5 ... die bonding material, 6 ... wiring conductor, 7 ... leader wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 貫通穴及び前記貫通穴の近傍で終る配線導体が
表面に設けられた配線基板と、前記配線基板の裏
面に前記貫通孔を塞いで選択的に貼りつけられた
熱伝導性の第１のフレームと、前記配線基板の裏
面に前記第１のフレームと離れて貼りつけられた
熱伝導性の第２のフレームとを含み、前記第１の
フレームの前記貫通穴部を部品搭載部として有す
ることを特徴とする混成集積回路基板。 a wiring board having a through hole and a wiring conductor that terminates in the vicinity of the through hole on its surface; and a thermally conductive first frame selectively attached to the back surface of the wiring board to cover the through hole. , comprising a second thermally conductive frame attached to the back surface of the wiring board apart from the first frame, and having the through-hole section of the first frame as a component mounting section. Hybrid integrated circuit board.
JP1987057646U 1987-04-15 1987-04-15 Pending JPS63164239U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987057646U JPS63164239U (en) 1987-04-15 1987-04-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987057646U JPS63164239U (en) 1987-04-15 1987-04-15

Publications (1)

Publication Number Publication Date
JPS63164239U true JPS63164239U (en) 1988-10-26

Family

ID=30887549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987057646U Pending JPS63164239U (en) 1987-04-15 1987-04-15

Country Status (1)

Country Link
JP (1) JPS63164239U (en)

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