JPH03101529U - - Google Patents
Info
- Publication number
- JPH03101529U JPH03101529U JP1990009482U JP948290U JPH03101529U JP H03101529 U JPH03101529 U JP H03101529U JP 1990009482 U JP1990009482 U JP 1990009482U JP 948290 U JP948290 U JP 948290U JP H03101529 U JPH03101529 U JP H03101529U
- Authority
- JP
- Japan
- Prior art keywords
- tab tape
- wiring board
- wiring
- conductive
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案に係る半導体装置用回路基板の
実施例を示す実装後の断面図、第２図は第１図の
要部の製造工程を示す断面図、第３図は第１図の
実装状態を示す断面図である。
１……タブテープ、２……配線基板、３……半
導体素子、５……導通スルーホール。
FIG. 1 is a sectional view after mounting showing an embodiment of the circuit board for a semiconductor device according to the present invention, FIG. 2 is a sectional view showing the manufacturing process of the main part of FIG. 1, and FIG. FIG. 3 is a cross-sectional view showing a mounted state. 1... Tab tape, 2... Wiring board, 3... Semiconductor element, 5... Conductive through hole.
Claims (1)
ボンデイング位置周りに配線基板を積層一体化し
、配線基板の配線とタブテープのリードとを導通
スルーホールで電気的に接続してなる半導体装置
用回路基板。 A circuit board for a semiconductor device, in which a wiring board is laminated and integrated around a bonding position where a semiconductor element of a tab tape is bonded, and the wiring of the wiring board and the lead of the tab tape are electrically connected by a conductive through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009482U JP2525353Y2 (en) | 1990-01-31 | 1990-01-31 | Circuit board for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009482U JP2525353Y2 (en) | 1990-01-31 | 1990-01-31 | Circuit board for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03101529U true JPH03101529U (en) | 1991-10-23 |
| JP2525353Y2 JP2525353Y2 (en) | 1997-02-12 |
Family
ID=31513082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990009482U Expired - Fee Related JP2525353Y2 (en) | 1990-01-31 | 1990-01-31 | Circuit board for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2525353Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129745A (en) * | 1989-10-16 | 1991-06-03 | Sumitomo Bakelite Co Ltd | Mounting of semiconductor device |
-
1990
- 1990-01-31 JP JP1990009482U patent/JP2525353Y2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129745A (en) * | 1989-10-16 | 1991-06-03 | Sumitomo Bakelite Co Ltd | Mounting of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2525353Y2 (en) | 1997-02-12 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |