JPH0396047U - - Google Patents

Info

Publication number
JPH0396047U
JPH0396047U JP469890U JP469890U JPH0396047U JP H0396047 U JPH0396047 U JP H0396047U JP 469890 U JP469890 U JP 469890U JP 469890 U JP469890 U JP 469890U JP H0396047 U JPH0396047 U JP H0396047U
Authority
JP
Japan
Prior art keywords
circuit board
integrated circuit
wiring pattern
multilayer circuit
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP469890U
Other languages
Japanese (ja)
Other versions
JP2591999Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990004698U priority Critical patent/JP2591999Y2/en
Publication of JPH0396047U publication Critical patent/JPH0396047U/ja
Application granted granted Critical
Publication of JP2591999Y2 publication Critical patent/JP2591999Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示す平面図、第２図
は第１図の一断面の断面図、第３図は従来の集積
回路パツケージの構造の一例を示す平面図、第４
図は第３図の一断面の断面図である。 １……外部リード端子、２……シームリング、
３……ふた、４，５，１２，１３……多層回路基
板、６……半導体素子、７，８……電気部品、９
，１０……ワイヤーボンデイング、１１……金属
板。 FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a sectional view of one section of FIG. 1, FIG. 3 is a plan view showing an example of the structure of a conventional integrated circuit package, and FIG.
The figure is a sectional view of one section of FIG. 3. 1...External lead terminal, 2...Seam ring,
3... Lid, 4, 5, 12, 13... Multilayer circuit board, 6... Semiconductor element, 7, 8... Electrical component, 9
, 10... wire bonding, 11... metal plate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周囲に配線パターンと部品接続用パターンとを
備え、中央部に半導体素子実装用の切り欠き部を
有する多層から成る多層回路基板の外周に前記配
線パターンと接続する外部接続用リード端子を、
底部に金属板を、上部にシームリングを有して一
体化して成ることを特徴とする集積回路のパツケ
ージの構造。 An external connection lead terminal connected to the wiring pattern is provided on the outer periphery of a multilayer circuit board consisting of a multilayer circuit board having a wiring pattern and a component connection pattern around the periphery and a notch for mounting a semiconductor element in the center.
An integrated circuit package structure characterized by an integrated circuit having a metal plate at the bottom and a seam ring at the top.
JP1990004698U 1990-01-22 1990-01-22 Integrated circuit package structure Expired - Lifetime JP2591999Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990004698U JP2591999Y2 (en) 1990-01-22 1990-01-22 Integrated circuit package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990004698U JP2591999Y2 (en) 1990-01-22 1990-01-22 Integrated circuit package structure

Publications (2)

Publication Number Publication Date
JPH0396047U true JPH0396047U (en) 1991-10-01
JP2591999Y2 JP2591999Y2 (en) 1999-03-10

Family

ID=31508432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990004698U Expired - Lifetime JP2591999Y2 (en) 1990-01-22 1990-01-22 Integrated circuit package structure

Country Status (1)

Country Link
JP (1) JP2591999Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011128140A (en) * 2009-11-19 2011-06-30 Dainippon Printing Co Ltd Sensor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62101234U (en) * 1985-12-16 1987-06-27
JPS6448039U (en) * 1987-09-21 1989-03-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62101234U (en) * 1985-12-16 1987-06-27
JPS6448039U (en) * 1987-09-21 1989-03-24

Also Published As

Publication number Publication date
JP2591999Y2 (en) 1999-03-10

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term