JPH03117833U - - Google Patents

Info

Publication number
JPH03117833U
JPH03117833U JP2671190U JP2671190U JPH03117833U JP H03117833 U JPH03117833 U JP H03117833U JP 2671190 U JP2671190 U JP 2671190U JP 2671190 U JP2671190 U JP 2671190U JP H03117833 U JPH03117833 U JP H03117833U
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
hybrid integrated
board
mounting land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2671190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2671190U priority Critical patent/JPH03117833U/ja
Publication of JPH03117833U publication Critical patent/JPH03117833U/ja
Pending legal-status Critical Current

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  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ本考案の一実施
例および他の実施例の要部平面図、第3図は従来
の混成集積回路の要部平面図である。 1,3……チツプ搭載ランド、2……切欠き、
4……突起、5……半導体チツプ、6……一番ピ
ン電極、7……ワイヤボンデイングランド。
1 and 2 are plan views of essential parts of one embodiment and another embodiment of the present invention, respectively, and FIG. 3 is a plan view of essential parts of a conventional hybrid integrated circuit. 1, 3... Chip mounting land, 2... Notch,
4...Protrusion, 5...Semiconductor chip, 6...First pin electrode, 7...Wire bonding ground.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 混成集積回路基板と、この基板上のチツプ搭載
ランドに搭載された半導体チツプとを含む混成集
積回路において、前記基板上のチツプ搭載ランド
の外周辺の一部分には、前記チツプの搭載方向を
示す目印となるための、前記チツプの外周図形よ
り稍々大きな相似形からずれた凸起または切欠き
が設けられていることを特徴とする混成集積回路
In a hybrid integrated circuit including a hybrid integrated circuit board and a semiconductor chip mounted on a chip mounting land on the board, a mark indicating the mounting direction of the chip is provided on a part of the outer periphery of the chip mounting land on the board. A hybrid integrated circuit characterized in that a protrusion or notch is provided which is slightly larger than the outer peripheral figure of the chip and deviates from a similar shape.
JP2671190U 1990-03-15 1990-03-15 Pending JPH03117833U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2671190U JPH03117833U (en) 1990-03-15 1990-03-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2671190U JPH03117833U (en) 1990-03-15 1990-03-15

Publications (1)

Publication Number Publication Date
JPH03117833U true JPH03117833U (en) 1991-12-05

Family

ID=31529592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2671190U Pending JPH03117833U (en) 1990-03-15 1990-03-15

Country Status (1)

Country Link
JP (1) JPH03117833U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008216820A (en) * 2007-03-06 2008-09-18 Funai Electric Co Ltd Liquid crystal panel fixation structure and liquid crystal television
JP2009265204A (en) * 2008-04-23 2009-11-12 Funai Electric Co Ltd Wall-hung display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008216820A (en) * 2007-03-06 2008-09-18 Funai Electric Co Ltd Liquid crystal panel fixation structure and liquid crystal television
JP2009265204A (en) * 2008-04-23 2009-11-12 Funai Electric Co Ltd Wall-hung display device

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