JPH02132961U - - Google Patents
Info
- Publication number
- JPH02132961U JPH02132961U JP1989043444U JP4344489U JPH02132961U JP H02132961 U JPH02132961 U JP H02132961U JP 1989043444 U JP1989043444 U JP 1989043444U JP 4344489 U JP4344489 U JP 4344489U JP H02132961 U JPH02132961 U JP H02132961U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- integrated circuit
- semiconductor integrated
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図および第２図はそれぞれ本考案の一実施
例の一部分の平面図およびＡ−Ａ′断面図、第３
図および第４図はそれぞれ従来の半導体集積回路
パツケージの一部分の平面図およびＢ−Ｂ′断面
図である。
１……グランド配線、１Ａ……パツケージグラ
ンドリード線、１Ｂ……グランドボンデイング線
、１Ｃ……グランド配線、２……電源配線、２Ａ
……パツケージ電源リード線、２Ｂ……電源ボン
デイング線、２Ｃ……電源配線、３……半導体集
積回路パツケージ、４……信号配線、４Ａ……パ
ツケージ信号リード線、４Ｂ……信号ボンデイン
グ線、５……半導体集積回路、６……ノイズ防止
コンデンサ、７……コンデンサ取付用パツド。
FIGS. 1 and 2 are a plan view and a cross-sectional view of a portion of an embodiment of the present invention, respectively, and FIG.
4 are a plan view and a sectional view taken along line B-B' of a part of a conventional semiconductor integrated circuit package, respectively. 1...Ground wiring, 1A...Package ground lead wire, 1B...Ground bonding wire, 1C...Ground wiring, 2...Power supply wiring, 2A
...Package power lead wire, 2B...Power bonding wire, 2C...Power supply wiring, 3...Semiconductor integrated circuit package, 4...Signal wiring, 4A...Package signal lead wire, 4B...Signal bonding wire, 5 ... Semiconductor integrated circuit, 6 ... Noise prevention capacitor, 7 ... Capacitor mounting pad.
Claims (1)
組合う櫛状に形成し、これらの配線対が電源ノイ
ズ防止用のコンデンサを構成することを特徴とす
る半導体集積回路パツケージ。 1. A semiconductor integrated circuit package characterized in that adjacent power supply wiring and ground wiring are formed in a comb-shape that interlocks with each other, and a pair of these wiring forms a capacitor for preventing power supply noise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989043444U JPH02132961U (en) | 1989-04-12 | 1989-04-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989043444U JPH02132961U (en) | 1989-04-12 | 1989-04-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02132961U true JPH02132961U (en) | 1990-11-05 |
Family
ID=31555858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989043444U Pending JPH02132961U (en) | 1989-04-12 | 1989-04-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02132961U (en) |
-
1989
- 1989-04-12 JP JP1989043444U patent/JPH02132961U/ja active Pending