JPS63200340U - - Google Patents
Info
- Publication number
- JPS63200340U JPS63200340U JP1987091503U JP9150387U JPS63200340U JP S63200340 U JPS63200340 U JP S63200340U JP 1987091503 U JP1987091503 U JP 1987091503U JP 9150387 U JP9150387 U JP 9150387U JP S63200340 U JPS63200340 U JP S63200340U
- Authority
- JP
- Japan
- Prior art keywords
- conductive wires
- cross
- lead frame
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案の実施例を示す導線のクロス部
分の拡大図、第2図A及び第2図Bは本考案の実
施例を示す側面図、第3図は他の実施例を示す断
面図、第4図及び第5図は従来例を示す平面図で
ある。
1はアイランド、2は外部リード、3はリード
フレーム、4は半導体素子、5は導線、6は導線
酸化治具、7は酸化膜。
Fig. 1 is an enlarged view of a cross section of conductive wires showing an embodiment of the invention, Figs. 2A and 2B are side views showing an embodiment of the invention, and Fig. 3 is a cross section showing another embodiment. 4 and 5 are plan views showing conventional examples. 1 is an island, 2 is an external lead, 3 is a lead frame, 4 is a semiconductor element, 5 is a conductor, 6 is a conductor oxidation jig, and 7 is an oxide film.
Claims (1)
搭載され、前記半導体素子と前記リードフレーム
の外部リードとを接続する導線が少なくとも一カ
所でクロス配置された半導体装置において、前記
導線がクロスされる部分の前記導線表面に導線酸
化治具を用いて酸化膜が形成されたことを特徴と
する半導体装置。 In a semiconductor device in which a semiconductor element is mounted on an island of a lead frame, and conductive wires connecting the semiconductor element and an external lead of the lead frame are arranged to cross each other at least in one place, the conductive wires are arranged at a portion where the conductive wires cross each other. A semiconductor device characterized in that an oxide film is formed on the surface using a conductor oxidation jig.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987091503U JPS63200340U (en) | 1987-06-15 | 1987-06-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987091503U JPS63200340U (en) | 1987-06-15 | 1987-06-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63200340U true JPS63200340U (en) | 1988-12-23 |
Family
ID=30952346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987091503U Pending JPS63200340U (en) | 1987-06-15 | 1987-06-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63200340U (en) |
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1987
- 1987-06-15 JP JP1987091503U patent/JPS63200340U/ja active Pending