JPS63140698U - - Google Patents
Info
- Publication number
- JPS63140698U JPS63140698U JP3263687U JP3263687U JPS63140698U JP S63140698 U JPS63140698 U JP S63140698U JP 3263687 U JP3263687 U JP 3263687U JP 3263687 U JP3263687 U JP 3263687U JP S63140698 U JPS63140698 U JP S63140698U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thin film
- integrated
- main body
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂは本考案の半導体装置の実施例１
の側面図、側面断面図である。第２図ａ，ｂは本
考案の半導体装置実施例２の断面図、側面図であ
る。
FIGS. 1a and 1b show Example 1 of the semiconductor device of the present invention.
They are a side view and a side sectional view. FIGS. 2a and 2b are a sectional view and a side view of a second embodiment of the semiconductor device of the present invention.
Claims (1)
の薄膜と半導体装置のリード線と電気的に接続し
一体となつていることを特徴とする半導体装置。 A semiconductor device characterized in that a conductive thin film is attached to a part of the surface of the main body, and the thin film is electrically connected to a lead wire of the semiconductor device so as to be integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3263687U JPS63140698U (en) | 1987-03-05 | 1987-03-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3263687U JPS63140698U (en) | 1987-03-05 | 1987-03-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63140698U true JPS63140698U (en) | 1988-09-16 |
Family
ID=30839504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3263687U Pending JPS63140698U (en) | 1987-03-05 | 1987-03-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140698U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007507108A (en) * | 2003-09-25 | 2007-03-22 | フリースケール セミコンダクター インコーポレイテッド | Method for forming semiconductor package and structure thereof |
| JP2014127707A (en) * | 2012-12-27 | 2014-07-07 | Toshiba Corp | Electronic component |
-
1987
- 1987-03-05 JP JP3263687U patent/JPS63140698U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007507108A (en) * | 2003-09-25 | 2007-03-22 | フリースケール セミコンダクター インコーポレイテッド | Method for forming semiconductor package and structure thereof |
| JP2014127707A (en) * | 2012-12-27 | 2014-07-07 | Toshiba Corp | Electronic component |