JPS63137955U - - Google Patents
Info
- Publication number
- JPS63137955U JPS63137955U JP1987028780U JP2878087U JPS63137955U JP S63137955 U JPS63137955 U JP S63137955U JP 1987028780 U JP1987028780 U JP 1987028780U JP 2878087 U JP2878087 U JP 2878087U JP S63137955 U JPS63137955 U JP S63137955U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- mounting table
- lead frame
- hole
- wire connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Description
第1図は本考案の第1の実施例にかかるリード
フレームの部分概略斜視図、第2図はこのリード
フレームを使用した半導体装置の断面図、第3図
は本考案の第2の実施例にかかるリードフレーム
の部分概略斜視図、第4図はこのリードフレーム
を使用した半導体装置の断面図、第5図は従来の
一般的なリードフレームの概略平面図である。
1…載置台、2…接続細条、3…リード線接続
部、4…貫通孔、5…半導体チツプ、6…樹脂、
14…貫通孔。
FIG. 1 is a partial schematic perspective view of a lead frame according to a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device using this lead frame, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor device using this lead frame, and FIG. 5 is a schematic plan view of a conventional general lead frame. DESCRIPTION OF SYMBOLS 1... Mounting table, 2... Connection strip, 3... Lead wire connection part, 4... Through hole, 5... Semiconductor chip, 6... Resin,
14...Through hole.
Claims (1)
続部とを有し、 上記載置台の半導体チツプ接触部に少なくとも
1つの貫通孔が形成されたことを特徴とするリー
ドフレーム。[Claims for Utility Model Registration] A device comprising a mounting table on which a semiconductor chip is placed and a lead wire connection part, and characterized in that at least one through hole is formed in the semiconductor chip contacting part of the mounting table. Lead frame.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987028780U JPS63137955U (en) | 1987-03-02 | 1987-03-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987028780U JPS63137955U (en) | 1987-03-02 | 1987-03-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63137955U true JPS63137955U (en) | 1988-09-12 |
Family
ID=30832058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987028780U Pending JPS63137955U (en) | 1987-03-02 | 1987-03-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63137955U (en) |
-
1987
- 1987-03-02 JP JP1987028780U patent/JPS63137955U/ja active Pending