JPS6274336U - - Google Patents
Info
- Publication number
- JPS6274336U JPS6274336U JP16694185U JP16694185U JPS6274336U JP S6274336 U JPS6274336 U JP S6274336U JP 16694185 U JP16694185 U JP 16694185U JP 16694185 U JP16694185 U JP 16694185U JP S6274336 U JPS6274336 U JP S6274336U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- frame
- protrusion
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例による半導体装置用
フレームの平面図、第２図はそのＸ―Ｘ線断面図
、第３図は従来フレームの平面図である。
１……フレーム、２……チツプ載置電極、３，
４……電極、５……ソルダ、６，７，８……細線
、１０……チツプ、１１……凸起部。なお図中同
一符号は同一又は相当部分を示す。
FIG. 1 is a plan view of a frame for a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line X--X, and FIG. 3 is a plan view of a conventional frame. 1...Frame, 2...Chip mounting electrode, 3,
4... Electrode, 5... Solder, 6, 7, 8... Thin wire, 10... Chip, 11... Convex portion. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
配線接続用の凸起部が形成されていることを特徴
とする半導体装置用フレーム。 1. A frame for a semiconductor device, comprising an electrode on which a semiconductor device is placed, and a protrusion for wiring connection formed on the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16694185U JPS6274336U (en) | 1985-10-30 | 1985-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16694185U JPS6274336U (en) | 1985-10-30 | 1985-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6274336U true JPS6274336U (en) | 1987-05-13 |
Family
ID=31098400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16694185U Pending JPS6274336U (en) | 1985-10-30 | 1985-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6274336U (en) |
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1985
- 1985-10-30 JP JP16694185U patent/JPS6274336U/ja active Pending