JPS6367251U - - Google Patents

Info

Publication number
JPS6367251U
JPS6367251U JP16174186U JP16174186U JPS6367251U JP S6367251 U JPS6367251 U JP S6367251U JP 16174186 U JP16174186 U JP 16174186U JP 16174186 U JP16174186 U JP 16174186U JP S6367251 U JPS6367251 U JP S6367251U
Authority
JP
Japan
Prior art keywords
package
circuit board
printed circuit
outer periphery
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16174186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16174186U priority Critical patent/JPS6367251U/ja
Publication of JPS6367251U publication Critical patent/JPS6367251U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A,Bは本考案の実施例を示した側面図
並びに平面図である。第2図は本考案によるパツ
ケージをプリント基板に搭載した様子を示す。第
3図は、従来のパツケージをプリント基板に搭載
した様子を示す。 1……本考案によるパツケージ形状、2……本
考案によるパツケージの階段状構造部分、3……
パツケージのピン、4……パツケージのキヤツプ
、5……プリント基板、6……従来のパツケージ
形状。
1A and 1B are a side view and a plan view showing an embodiment of the present invention. FIG. 2 shows how the package according to the present invention is mounted on a printed circuit board. FIG. 3 shows how a conventional package is mounted on a printed circuit board. 1...Package shape according to the present invention, 2...Step-like structure portion of the package according to the present invention, 3...
Package pin, 4...Package cap, 5...Printed circuit board, 6...Conventional package shape.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ピン・グリツド・アレイタイプの集積回路パツ
ケージに於て、該パツケージの外周部のプリント
基板装着面側が階段状構造とされていることを特
徴とする集積回路パツケージ。
1. A pin grid array type integrated circuit package, characterized in that the outer periphery of the package on the side on which a printed circuit board is mounted has a step-like structure.
JP16174186U 1986-10-21 1986-10-21 Pending JPS6367251U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16174186U JPS6367251U (en) 1986-10-21 1986-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16174186U JPS6367251U (en) 1986-10-21 1986-10-21

Publications (1)

Publication Number Publication Date
JPS6367251U true JPS6367251U (en) 1988-05-06

Family

ID=31088338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16174186U Pending JPS6367251U (en) 1986-10-21 1986-10-21

Country Status (1)

Country Link
JP (1) JPS6367251U (en)

Similar Documents

Publication Publication Date Title
JPS6367251U (en)
JPH0328742U (en)
JPS62114773U (en)
JPS62104453U (en)
JPH03117833U (en)
JPS6387841U (en)
JPS61111160U (en)
JPS6252968U (en)
JPS62103262U (en)
JPS6333657U (en)
JPS6245868U (en)
JPS61195054U (en)
JPS62151777U (en)
JPS6232625U (en)
JPS6359344U (en)
JPS6221550U (en)
JPS62163939U (en)
JPH01169037U (en)
JPH0247051U (en)
JPS6183055U (en)
JPS6181161U (en)
JPS6324847U (en)
JPH01130268U (en)
JPS63140646U (en)
JPS6328279U (en)