JPS62104453U - - Google Patents
Info
- Publication number
- JPS62104453U JPS62104453U JP1985196709U JP19670985U JPS62104453U JP S62104453 U JPS62104453 U JP S62104453U JP 1985196709 U JP1985196709 U JP 1985196709U JP 19670985 U JP19670985 U JP 19670985U JP S62104453 U JPS62104453 U JP S62104453U
- Authority
- JP
- Japan
- Prior art keywords
- pin grid
- lead terminal
- utility
- convex portion
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Description
第１図、第２図、第３図はそれぞれ本考案を示
す図である。
１……リード端子、２……ピングリツドパツケ
ージ本体、３……ピン・グリツド・パツケージと
一体にて成形された凸部、第３図に於いて、４…
…集積回路、５……プリント基板。
FIG. 1, FIG. 2, and FIG. 3 are diagrams each showing the present invention. 1...Lead terminal, 2...Pin grid package body, 3...Convex part molded integrally with the pin grid package, in Fig. 3, 4...
...Integrated circuit, 5...Printed circuit board.
Claims (1)
、リード端子面全面に凸部を設けたことを特徴と
するピン・グリツド・アレイ・パツケージ。 A pin grid array package characterized in that a convex portion is provided on the entire surface of the lead terminal surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985196709U JPS62104453U (en) | 1985-12-20 | 1985-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985196709U JPS62104453U (en) | 1985-12-20 | 1985-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62104453U true JPS62104453U (en) | 1987-07-03 |
Family
ID=31155780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985196709U Pending JPS62104453U (en) | 1985-12-20 | 1985-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104453U (en) |
-
1985
- 1985-12-20 JP JP1985196709U patent/JPS62104453U/ja active Pending