JP2591999Y2 - Integrated circuit package structure - Google Patents
Integrated circuit package structureInfo
- Publication number
- JP2591999Y2 JP2591999Y2 JP1990004698U JP469890U JP2591999Y2 JP 2591999 Y2 JP2591999 Y2 JP 2591999Y2 JP 1990004698 U JP1990004698 U JP 1990004698U JP 469890 U JP469890 U JP 469890U JP 2591999 Y2 JP2591999 Y2 JP 2591999Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit board
- semiconductor element
- package structure
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は集積回路のパッケージの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the structure of an integrated circuit package.
従来、半導体素子とその周辺回路を含めて小型化し、
モジュールとする集積回路のパッケージの構造として
は、第３図と第４図とに示す様に、半導体素子６を配線
パターンおよび部品接続用パターンを備えた多層回路基
板13上に搭載し、その周辺回路となる電気部品7,8も同
一基板13上に搭載した後半導体素子６と多層回路基板13
とをワイヤボンディング10にて接続を行なった回路基板
を、外周に外部接続用リード端子１を有し、金属板11を
底部とする集積回路パッケージに収容し、パッケージと
多層回路基板13との接続を再び、ワイヤーボンディング
９にて行った構造が一般的に採用されている。Conventionally, miniaturization including the semiconductor element and its peripheral circuit,
As shown in FIGS. 3 and 4, the package structure of the integrated circuit as a module is such that the semiconductor element 6 is mounted on a multilayer circuit board 13 provided with a wiring pattern and a component connection pattern, and the periphery thereof. After the electrical components 7 and 8 to be circuits are mounted on the same substrate 13, the semiconductor element 6 and the multilayer circuit substrate 13 are mounted.
Is connected by wire bonding 10 and housed in an integrated circuit package having an external connection lead terminal 1 on the outer periphery and a metal plate 11 at the bottom, and connecting the package to the multilayer circuit board 13. Is performed again by the wire bonding 9.
上述した従来の集積回路のパッケージの構造では、半
導体から外部リード端子までの電気信号の経路が半導体
素子→ワイヤーボンディング→多層回路基板→ワイヤー
ボンディング→パッケージ→外部リード端子となってい
るので、使用周波数が高くなると接続部の特性インピー
ダンスの不整合が発生し、特性劣化の原因となる。特に
ワイヤーボンディング部は特性のインピーダンスの整合
が困難であり、高周波領域の使用に支障をきたしてい
る。また半導体素子に加わる熱ストレスが多回路基板に
13に固定する時と、多層回路基板13をパッケージの底部
に固定する時の二度にわたるため好ましくなく、それぞ
れ固定する際の半田の溶融温度に差をつける必要がある
など工程が複雑となる。また、半導体素子の消費電力が
大きい場合多層回路基板を通しての熱放散となるため全
体の熱抵抗が高くなり、温度上昇が大きくなるという欠
点がある。In the above-described conventional package structure of an integrated circuit, the electric signal path from the semiconductor to the external lead terminals is a semiconductor element → wire bonding → multilayer circuit board → wire bonding → package → external lead terminals. Is increased, characteristic impedance mismatching of the connecting portion occurs, which causes characteristic deterioration. In particular, it is difficult to match the characteristic impedance of the wire bonding portion, which hinders use in a high frequency region. In addition, thermal stress applied to semiconductor elements can
This is not preferable because it is performed twice when the multi-layer circuit board 13 is fixed to the bottom of the package, and when the multi-layer circuit board 13 is fixed to the bottom of the package. Further, when the power consumption of the semiconductor element is large, heat is dissipated through the multilayer circuit board, so that the overall thermal resistance is increased and the temperature rise is disadvantageously increased.
本考案の集積回路のパッケージの構造は、周囲に配線
パターンと部品接続用パターンとを備え、中央部に半導
体素子実装用の切り欠き部を有する多層から成る多層回
路基板の外周に前記配線パターンと接続する外部接続用
リード端子を、底部に金属板を、上部にシームリングを
有して一体化して成っている。The structure of the package of the integrated circuit of the present invention is provided with a wiring pattern and a component connection pattern on the periphery, and the wiring pattern on the outer periphery of a multilayer circuit board including a multilayer having a cutout for mounting a semiconductor element in the center. The external connection lead terminals to be connected are integrally formed with a metal plate at the bottom and a seam ring at the top.
次に、本考案について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本考案の一実施例を示す平面図、第２図は第
１図の一断面の断面図である。FIG. 1 is a plan view showing one embodiment of the present invention, and FIG. 2 is a sectional view of one section of FIG.
第１図，第２図において、本実施例は中央部に切り欠
き部15を備えた多層回路基板4,5内には目的に合った配
線パターン14が形成され、上部に部品接続用パターンを
設けている。1 and 2, in the present embodiment, a wiring pattern 14 suitable for the purpose is formed in multilayer circuit boards 4, 5 having a cutout 15 in the center, and a component connection pattern is formed on the upper part. Provided.
多層回路基板４の底部には放熱用の金属板11が備えて
あり、半導体素子６はこの金属板上に実装される。多層
回路基板４と半導体素子６はワイヤーボンディング９に
て接続され、多層回路基板４の内部に設けられた配線パ
ターン14を介して外部接続用の外部リード端子１や多層
回路基板５の上部の部品7,8と接続される。多層回路基
板５の上部の周囲には封止するためのふた３をシームす
るためのシームリング２が備えてある。A metal plate 11 for heat radiation is provided at the bottom of the multilayer circuit board 4, and the semiconductor element 6 is mounted on the metal plate. The multilayer circuit board 4 and the semiconductor element 6 are connected by wire bonding 9, and the external lead terminals 1 for external connection and the components on the multilayer circuit board 5 are connected via a wiring pattern 14 provided inside the multilayer circuit board 4. Connected to 7,8. A seam ring 2 for seaming a lid 3 for sealing is provided around the upper part of the multilayer circuit board 5.
以上説明したように本考案は、半導素子から外部接続
用リード端子までの電気信号の経路にワイヤーボンディ
ング部が減るようにしたので、特性インピーダンスの整
合がし易くなり、高周波領域での使用が可能となる他
に、半導体素子を実装する回数が１回で済むため、熱ス
トレスが少なくなって信頼性の向上が計れ、さらに、金
属板に直接搭載するため熱抵抗が低くなり、温度上昇を
低くおさえることができる効果がある。As described above, in the present invention, since the wire bonding portion is reduced in the path of the electric signal from the semiconductor element to the external connection lead terminal, matching of the characteristic impedance is facilitated, and use in a high frequency region is facilitated. In addition to this, the semiconductor element can be mounted only once, which reduces thermal stress and improves reliability. Furthermore, since the semiconductor element is directly mounted on a metal plate, the thermal resistance decreases and the temperature rises. There is an effect that can be kept low.
第１図は本考案の実施例を示す平面図、第２図は第１図
の一断面の断面図、第３図は従来の集積回路パッケージ
の構造の一例を示す平面図、第４図は第３図の一断面の
断面図である。 １…外部リード端子、２…シームリング、３…ふた、4,
5,12,13…多層回路基板、６…半導体素子、7,8…電気部
品、9,10…ワイヤーボンディング、11…金属板。1 is a plan view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of one section of FIG. 1, FIG. 3 is a plan view showing an example of the structure of a conventional integrated circuit package, and FIG. FIG. 4 is a sectional view of one section of FIG. 3; 1: external lead terminal, 2: seam ring, 3: lid, 4,
5,12,13 ... Multilayer circuit board, 6 ... Semiconductor element, 7,8 ... Electrical component, 9,10 ... Wire bonding, 11 ... Metal plate.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/02 C H01L 21/60 A ──────────────────────────────────────────────────の Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 23/02 C H01L 21/60 A
Claims (1)
とを備え、中央部に半導体素子実装用の切り欠き部を有
する多層から成る多層回路基板の外周に前記配線パター
ンと接続する外部接続用リード端子を、底部に金属板
を、上部にシームリングを有して一体化して成ることを
特徴とする集積回路のパッケージの構造。An external connection lead connected to the wiring pattern on the outer periphery of a multilayer circuit board comprising a multilayer having a wiring pattern and a component connection pattern on a periphery thereof and a cutout for mounting a semiconductor element in a central portion. A package structure for an integrated circuit, comprising a terminal, a metal plate at the bottom, and a seam ring at the top, which are integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990004698U JP2591999Y2 (en) | 1990-01-22 | 1990-01-22 | Integrated circuit package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990004698U JP2591999Y2 (en) | 1990-01-22 | 1990-01-22 | Integrated circuit package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0396047U JPH0396047U (en) | 1991-10-01 |
| JP2591999Y2 true JP2591999Y2 (en) | 1999-03-10 |
Family
ID=31508432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990004698U Expired - Lifetime JP2591999Y2 (en) | 1990-01-22 | 1990-01-22 | Integrated circuit package structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2591999Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011128140A (en) * | 2009-11-19 | 2011-06-30 | Dainippon Printing Co Ltd | Sensor device and method of manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341475Y2 (en) * | 1985-12-16 | 1991-08-30 | ||
| JPS6448039U (en) * | 1987-09-21 | 1989-03-24 |
-
1990
- 1990-01-22 JP JP1990004698U patent/JP2591999Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011128140A (en) * | 2009-11-19 | 2011-06-30 | Dainippon Printing Co Ltd | Sensor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0396047U (en) | 1991-10-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |